公开(公告)号：US3825894A

公开(公告)日：1974-07-23

申请号：US40045173

申请日：1973-09-24

Applicant: IBM

Inventor： JOHNSON A

IPC: G06F11/22 ,  G06F11/10 ,  G06F11/16 ,  H04L1/10

CPC classification number: H03K19/0075 ,  G06F11/10 ,  H03K19/20

Abstract: A series of self-checking error checking circuits are disclosed for checking two or more independent sets of parity coded data lines. Each data signal set includes any logical combination of binary ''''1''s'''' and ''''0''s'''' and at least one parity bit. Each checking circuit comprises two Exclusive-OR tree circuits wherein each tree obtains its inputs from different input lines of each set of independent data lines whereby complementing outputs are produced by the two tree circuits for any correct signal set when the checker is error free. Any error in the data will cause the two outputs to be the same. Malfunctions or failures in the checking circuit are checked by certain legitimate code signals which similarly cause an error representation in the output of the checker.

Abstract translation: 公开了一系列自检错误检查电路，用于检查两个或多个独立的奇偶编码数据线组。 每个数据信号组包括二进制“1”和“0”的任何逻辑组合和至少一个奇偶校验位。 每个检查电路包括两个异或树电路，其中每个树从每组独立数据线的不同输入线获得其输入，由此当检验器无错误时由两个树电路产生用于任何正确的信号组的补充输出。 数据中的任何错误将导致两个输出相同。 检查电路中的故障或故障由某些合法的代码信号进行检查，类似地在检验器的输出中引起错误表示。

公开(公告)号：US3812290A

公开(公告)日：1974-05-21

申请号：US18760771

申请日：1971-10-08

Applicant: SIEMENS AG

Inventor： LUTZ R

IPC: H04L1/00 ,  H04L1/10

CPC classification number: H04L1/00

Abstract: A system for indicating parity-disturbing interferences in transmissions for teleprinters wherein the teleprinters print a special symbol to indicate such interferences including an electronic receiving circuit having electronic means for recoding received symbols which result in a non-parity condition during conversion, recoding providing a predetermined code combination for conversion by a printer into a special symbol, either a smear symbol or a space.

公开(公告)号：US3811108A

公开(公告)日：1974-05-14

申请号：US36478273

申请日：1973-05-29

Applicant: HONEYWELL INF SYSTEMS

Inventor： HOWELL T

IPC: H03M13/00 ,  G06F7/00 ,  G06F7/76 ,  G06F11/10 ,  H03M13/17 ,  H04L1/10

CPC classification number: H03M13/618 ,  H03M13/175 ,  H03M13/6516

Abstract: A method and apparatus is disclosed in which reversible cyclic encoding is used to enable reverse error identification. Encoding and decoding is performed in essentially a conventional manner, except that the coding conforms to a reversible cyclic generator polynomial. In the preferred embodiment, a linear feedback shift register is augmented with logic gates which enables the reversing of syndrome bits for subsequent error identification cycling in the event an error is detected.

Abstract translation: 公开了一种方法和装置，其中使用可逆循环编码来实现反向错误识别。 除了编码符合可逆循环生成多项式之外，基本上以常规方式执行编码和解码。 在优选实施例中，线性反馈移位寄存器用逻辑门增加，逻辑门使得能够在检测到错误的情况下对用于随后的错误识别循环的校正位进行反转。

公开(公告)号：US3805236A

公开(公告)日：1974-04-16

申请号：US32101573

申请日：1973-01-04

Applicant: THOMSON CSF

Inventor： BATTAIL G

IPC: H04L1/00 ,  H03K13/00 ,  H04L1/10

CPC classification number: H04L1/0059

Abstract: A plurality of complex replicas, or estimates, of each transmitted information bit, based on the parity-check equations, are formed in addition to the simple replica which the corresponding received information bit constitutes. To each replica is associated a likelihood magnitude of the form logm(1P)/P where P is the probability of the replica being erroneous. The decision is made by an algebraic adder forming the sum of the likelihoods of different estimates of the information bit, those likelihoods being associated with a plus or minus sign according to whether the binary value of the replica is 0 or 1. The sign of the sum gives the decoded value, and the absolute value of the sum, the likelihood of the decoded value.

Abstract translation: 除了对应的接收信息位构成的简单副本之外，还基于奇偶校验方程形成每个发送的信息位的多个复合副本或估计。 对于每个复制品与logm（1-P）/ P的形式的似然值相关联，其中P是复制品是错误的概率。

公开(公告)号：US3745525A

公开(公告)日：1973-07-10

申请号：US3745525D

申请日：1971-12-15

Applicant: IBM

Inventor： HONG S ,  PATEL A

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00 ,  H03M13/19 ,  H04L1/10 ,  G08C25/00

CPC classification number: H03M13/19

Abstract: An error correcting system is provided for information sequences divided into bytes of b bits each. The information is encoded in accordance with an H matrix consisting of a predetermined number of submatrices, each of which operates on distinct partitioned portions of the sequence of message bytes. Each of the submatrices are concatenated iteratively by b so that the submatrices can be designated by Hr,b; H(r b),b; H(r 2b),b . . . H(2b c),b where r kb+c and 0

公开(公告)号：US3602886A

公开(公告)日：1971-08-31

申请号：US3602886D

申请日：1968-07-25

Applicant: IBM

Inventor： CARTER WILLIAM C ,  SCHNEIDER PETER R

IPC: G06F11/10 ,  H03K13/34 ,  H03K5/18 ,  H04L1/10

CPC classification number: G06F11/10

Abstract: A series of self-checking error checking circuits are disclosed for checking conventional parity coded data lines. The data signal set includes any logical combination of binary ''''1''s'''' and ''''0''s'''' and at least one parity bit. The circuit comprises at least 2 exclusive OR tree circuits wherein each tree obtains its inputs from different input lines whereby complementing outputs are produced by the two tree circuits for any correct signal set and wherein the checker is error free. Any error in the data will cause the two outputs to be the same. Malfunctions or failures in the checking circuit are checked by certain legitimate code signals which similarly cause an error representation in the output of the checker.

公开(公告)号：US3593275A

公开(公告)日：1971-07-13

申请号：US3593275D

申请日：1968-07-09

Applicant: SIEMENS AG

Inventor： PUMPE GERHARD

IPC: H03M13/51 ,  H04L1/04 ,  G08C25/00 ,  H04L1/10

CPC classification number: H03M13/51

Abstract: An error recognition process for a system in which data is transmitted in a one out of m different modulation characteristics (e.g. frequencies) code and wherein errors at the transmitter, or in the transmission system can cause a plurality of modulation characteristics to exist simultaneously at the receiver. The method of the invention takes advantage of the fact that modulation products outside of the assigned frequency band result when two different modulation characteristics are combined in a nonlinear device. Frequencies outside of the assigned band are detected to furnish an error voltage which blocks the decoded output at the receiver to prevent errors.

公开(公告)号：US3588819A

公开(公告)日：1971-06-28

申请号：US3588819D

申请日：1968-09-18

Applicant: BELL TELEPHONE LABOR INC

Inventor： TONG SHIH Y

IPC: H03M13/23 ,  H04L1/00 ,  G08C25/00 ,  H04L1/10

CPC classification number: H04L1/0059 ,  H03M13/23

Abstract: INFORMATION CHARACTERS OF L-BIT LENGTH ARE ENCODED IN A CONVOLUTION CODE OF RATE UP TO (2K-1)/2K, (WHERE 2 -1 IS AN EVEN MULTIPLE OF 2K-1) AND THEN TRANSMITTED OVER A COMMUNICATION CHANNEL TO A RECEIVING TERMINAL. THE RECEIVED CHARACTERS ARE PROCESSED TO (1) OBTAIN TWO PARTIAL SYNDROMES S0 AND S1 ASSOCIATED WITH THE TWO MOST RECENTLY RECEIVED BLOCKS OF CHARACTERS, EACH BLOCK CONTAINING 2 CHARACTERS, AND (2) DETERMINE CHARACTER ERASURES, I.E., THE POSITION OF ERRORS. DETERMINATION OF CHARACTER ERASURES IS DONE BY PERFORMING SIGNAL QUALITY CHECKS ON THE CHARACTERS SUCH AS NULLZONE DETECTION. THE TWO SYNDROMES SO AND S1 ARE THEN UTILIZED TO CORRECT THE CHARACTER ERASURES. SIGNAL-CHARACTER ERASURES IN ANY 2-CHARACTER BLOCK CAN BE CORRECTED WITHOUT THE REQUIREMENT OF A GUARD SPACE. IN ADDITION, DOUBLE-CHARACTER ERASURES IN ANY 2 -CHARACTER BLOCK CAN BE CORRECTED PROVIDED THE SUBSEQUENT BLOCK IS ERROR FREE.

公开(公告)号：US3576952A

公开(公告)日：1971-05-04

申请号：US3576952D

申请日：1969-01-06

Applicant: NEDERLANDEN STAAT ,  TEN DEZE VERTEGENWOORDIGD DOOR

Inventor： DUUREN HENDRIK CORNELIS ANTHON

IPC: H04L1/00 ,  H04L1/10

CPC classification number: H04L1/0041 ,  H04L1/0045 ,  H04L1/0063 ,  H04L1/1829

Abstract: A multielement code telecommunication system comprising first converting each code signal into a constant ratio 1-bit/0-bit signal, storing a predetermined successive number of such converted code signals in shift registers to form a group, and forming a test signal by modulo 2 adding the bits in said group of signals which test signal is transmitted with and after each said group to form a block of signals; receiving and storing in shift registers each signal in said group, testing each signal as it is received and if one and only one signal in said group is found mutilated or erroneous, clearing the shift register in which that erroneous signal is stored and reconstructing therein the correct signal from said test signal and the other correctly received signals in that group; and lastly reconverting said correct group of signals and transferring them from printing registers successively to a printer.

公开(公告)号：US3573726A

公开(公告)日：1971-04-06

申请号：US3573726D

申请日：1968-09-26

Applicant: COMPUTER IND INC

Inventor： TOWELL LEROY D ,  SCOTT HARRY K

IPC: G06F11/08 ,  H03M13/09 ,  G08C25/00 ,  H04L1/10

CPC classification number: H03M13/09 ,  G06F11/08

Abstract: This invention relates, in general, to error detection for blocks of binary data, and more particularly relates to the transmission of a uniquely modified and check sum accumulated error identifying word, together with detection circuitry at the receiver location which senses the unique word and thereby verifies or negates that a block of data was correctly transmitted and received. In one preferred embodiment of the invention disclosed herein, a method and apparatus is disclosed for generating at a transmitting station, an error-checking word. The error-checking word is generated by making, in response to random binary bit sequences, unique modifications in its content. For example, one such unique modification in the word''s content is made in response to the number of frames in the block of data to be transmitted. Another unique modification of the error word''s content is made each time a check sum on a bit-by-bit basis exceeds the modulus, i.e. total bit-plus-bit capacity available in the error word. The error word''s content is subject to yet another unique modification, in response to the occurrence of a multibit word, within an overall block of data words, containing all ZERO''s. In one particular embodiment the complement of this error word is generated and sent to the receiver as the final word after a data block has been transmitted. Another essentially identical error-check summing circuit at the receiver station accumulates another error word. The receiver error-check word, when summed with the complemented error-check word from the transmitter has a predictable total when all data in the block has been transmitted and received error-free. If a sum other than that predicted is obtained at the receiver, then the received data contained an error.