公开(公告)号：US3573726A

公开(公告)日：1971-04-06

申请号：US3573726D

申请日：1968-09-26

Applicant: COMPUTER IND INC

Inventor： TOWELL LEROY D ,  SCOTT HARRY K

IPC: G06F11/08 ,  H03M13/09 ,  G08C25/00 ,  H04L1/10

CPC classification number: H03M13/09 ,  G06F11/08

Abstract: This invention relates, in general, to error detection for blocks of binary data, and more particularly relates to the transmission of a uniquely modified and check sum accumulated error identifying word, together with detection circuitry at the receiver location which senses the unique word and thereby verifies or negates that a block of data was correctly transmitted and received. In one preferred embodiment of the invention disclosed herein, a method and apparatus is disclosed for generating at a transmitting station, an error-checking word. The error-checking word is generated by making, in response to random binary bit sequences, unique modifications in its content. For example, one such unique modification in the word''s content is made in response to the number of frames in the block of data to be transmitted. Another unique modification of the error word''s content is made each time a check sum on a bit-by-bit basis exceeds the modulus, i.e. total bit-plus-bit capacity available in the error word. The error word''s content is subject to yet another unique modification, in response to the occurrence of a multibit word, within an overall block of data words, containing all ZERO''s. In one particular embodiment the complement of this error word is generated and sent to the receiver as the final word after a data block has been transmitted. Another essentially identical error-check summing circuit at the receiver station accumulates another error word. The receiver error-check word, when summed with the complemented error-check word from the transmitter has a predictable total when all data in the block has been transmitted and received error-free. If a sum other than that predicted is obtained at the receiver, then the received data contained an error.