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3409 条记录 (耗时 0.031 秒)

    STRESS REDUCTION ON STACKED TRANSISTOR CIRCUITS
    94.
    发明公开
    STRESS REDUCTION ON STACKED TRANSISTOR CIRCUITS 审中-公开

    公开(公告)号：US20230238959A1

    公开(公告)日：2023-07-27

    申请号：US18131009

    申请日：2023-04-05

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Erkan Bilhan ,  Francisco A. Cano

    IPC分类号： H03K19/003 ,  H03K19/20

    CPC分类号： H03K19/00315 ,  H03K19/20

    摘要： A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.

    Latch circuit
    95.
    发明授权
    Latch circuit 有权

    公开(公告)号：US11705893B2

    公开(公告)日：2023-07-18

    申请号：US17608401

    申请日：2021-03-09

    申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

    发明人： KeJun Wang

    IPC分类号： H03K3/037 ,  G11C17/16 ,  G11C17/18 ,  H03K19/20

    CPC分类号： H03K3/037 ,  G11C17/16 ,  G11C17/18 ,  H03K19/20

    摘要： A latch circuit includes a latch module, a set control module, a reset control module and a clock module, wherein the latch module is employed for latching data input by a data module, the set control module is employed for controlling the latch module to output a high-level signal, the reset control module is employed for controlling the latch module to output a low-level signal, and the clock module is employed for providing a readout clock signal to the latch module.

    Semiconductor device
    97.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11695415B2

    公开(公告)日：2023-07-04

    申请号：US17560821

    申请日：2021-12-23

    申请人： LAPIS TECHNOLOGY CO., LTD.

    发明人： Shouhei Yamamoto

    IPC分类号： H03K17/00 ,  H03K17/687 ,  H03K19/20 ,  H03K17/22 ,  H03K3/012

    CPC分类号： H03K17/6872 ,  H03K3/012 ,  H03K17/22 ,  H03K17/6874 ,  H03K19/20

    摘要： A power-on reset circuit 10 has: an enhancement-type PMOS transistor P1 whose source is connected to VDD and whose drain is connected to node VJG; a depletion-type NMOS transistor D1 whose drain is connected to the node VJG; a first resistor portion having resistors R1, R2 that are connected in series, and whose one end is connected to a source of the depletion-type NMOS transistor D1, and whose another end is connected to GND, and at which a region between the resistors R1, R2 is connected to a gate of the enhancement-type PMOS transistor P1; and an inverter whose input is connected to the node VJG, and that outputs a reset signal.

    SYSTEMS AND METHODS FOR QUARTER RATE SERIALIZATION
    98.
    发明公开
    SYSTEMS AND METHODS FOR QUARTER RATE SERIALIZATION 审中-公开

    公开(公告)号：US20230208423A1

    公开(公告)日：2023-06-29

    申请号：US17825378

    申请日：2022-05-26

    申请人： Samsung Electronics Co., Ltd.

    发明人： Umamaheswara Reddy KATTA ,  Tamal DAS

    IPC分类号： H03K19/0185 ,  H03K19/017 ,  H03K19/094 ,  H03K19/20

    CPC分类号： H03K19/01855 ,  H03K19/01742 ,  H03K19/0941 ,  H03K19/20

    摘要： A method, implemented in a serializer for quarter rate serialization, is disclosed. The method includes receiving a plurality of in-phase and quarter-phase clock signals defining a quarter phase clock. The method includes receiving a quarter rate data input and sequentially outputting data in accordance with the quarter phase clock. The method includes receiving at least one data input from amongst the quarter rate input and outputting a first logical output in accordance with the in-phase clock signal and the quarter-phase clock signal. The method includes receiving said at least one data input and outputting a second logical output in accordance a complementary in-phase clock signal and a complementary quarter-phase clock signal. The method includes outputting, an output associated with the branch.

    Architecture for analog multiplier-accumulator with binary weighted charge transfer capacitors
    99.
    发明授权
    Architecture for analog multiplier-accumulator with binary weighted charge transfer capacitors 有权

    公开(公告)号：US11689213B2

    公开(公告)日：2023-06-27

    申请号：US17334782

    申请日：2021-05-30

    申请人： Ceremorphic, Inc.

    发明人： Martin Kraemer ,  Ryan Boesch ,  Wei Xiong

    IPC分类号： H03M3/00 ,  H03M3/04 ,  G06J1/00 ,  H03M1/38 ,  H03K19/20

    CPC分类号： H03M3/04 ,  G06J1/00 ,  H03M1/38 ,  H03K19/20

    摘要： An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspect of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor to form an analog multiplication product as a charge applied to the differential charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

    FIXED BINARY ADDER WITH SMALL AREA AND METHOD OF DESIGNING THE SAME
    100.
    发明公开
    FIXED BINARY ADDER WITH SMALL AREA AND METHOD OF DESIGNING THE SAME 审中-公开

    公开(公告)号：US20230195415A1

    公开(公告)日：2023-06-22

    申请号：US17831093

    申请日：2022-06-02

    申请人： SK hynix Inc.

    发明人： Seong Ju LEE

    IPC分类号： G06F7/501 ,  G06F7/499 ,  H03K19/20

    CPC分类号： G06F7/501 ,  G06F7/49942 ,  H03K19/20

    摘要： A fixed binary adder adds an “N”-bit second operand to a first operand having an “N”-bit fixed value (N=2M, M is a natural number) to generate “N+1”-bit output data. The fixed binary adder includes a plurality of transfer logic stages each configured with at least one logic gate, and a summation addition logic configured to generate the “N+1”-bit output data by using the “N”-bit second operand and transfer data that is generated through the plurality of transfer logic stages. The logic gate is configured with one of an AND gate, an OR gate, and a buffer gate.