公开(公告)号：US5624861A

公开(公告)日：1997-04-29

申请号：US681512

申请日：1996-07-23

Applicant: Tsukasa Shibuya

Inventor： Tsukasa Shibuya

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L21/86 ,  H01L21/786

CPC classification number: H01L27/1214 ,  Y10S438/911

Abstract: A manufacturing method of a semiconductor device includes the steps of depositing a metallic film (light-shielding film), an insulating film and a semiconductor film in this order on an insulating substrate, and after patterning the insulating film and the semiconductor film in a predetermined shape, oxidizing an exposed region of the metallic film using the insulating film and the semiconductor film as a mask. As a result, the light-shielding film composed of the metallic film is formed so as to cover the semiconductor film to block light from an external portion. The manufacturing method permits a process of forming a resist pattern for use in forming the light-shielding film and a process of etching the light-shielding film to be omitted, thereby reducing the required number of processes. Moreover, as a level difference is not generated around the light-shielding film, a generation of a level difference on the semiconductor film can be prevented. Furthermore, as the light-shielding film can be formed completely overlapped with the semiconductor film, a reduction in a display region of the semiconductor device can be avoided, thereby improving an aperture ratio.

Abstract translation: 半导体器件的制造方法包括以下步骤：在绝缘基板上依次沉积金属膜（遮光膜），绝缘膜和半导体膜，并且在预定的绝缘膜和半导体膜图案化之后 使用绝缘膜和半导体膜作为掩模来氧化金属膜的暴露区域。 结果，由金属膜构成的遮光膜形成为覆盖半导体膜以阻挡来自外部的光。 制造方法允许形成用于形成遮光膜的抗蚀剂图案的处理和要被省略的蚀刻光屏蔽膜的工艺，从而减少所需的处理次数。 此外，由于在遮光膜周围不产生电平差，因此可以防止在半导体膜上产生电平差。 此外，由于遮光膜可以与半导体膜完全重叠，所以可以避免半导体器件的显示区域的减少，从而提高孔径比。

公开(公告)号：US5587597A

公开(公告)日：1996-12-24

申请号：US728917

申请日：1991-07-11

Applicant: Ronald E. Reedy ,  Graham A. Garcia ,  Isaac Lagnado

Inventor： Ronald E. Reedy ,  Graham A. Garcia ,  Isaac Lagnado

IPC: H01L21/768 ,  H01L21/86 ,  H01L23/482 ,  H01L27/12 ,  H01L29/04 ,  H01L31/0392 ,  H01L31/062

CPC classification number: H01L23/4825 ,  H01L21/76889 ,  H01L21/86 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/147

Abstract: A process for developing conductive interconnect regions between integrated circuit semiconductor devices formed on an insulating substrate utilizes the semiconductor material itself for formation of device interconnect regions.A patterned layer of semiconductor material is formed directly on the surface of an insulating substrate. The patterned layer includes regions where semiconductor devices are to be formed and regions which are to be used to interconnect terminals of predetermined ones of the semiconductor devices. After forming the semiconductor devices in selected regions of the semiconductor material, the regions of the semiconductor material patterned for becoming interconnects are converted to a metallic compound of the semiconductor material.

Abstract translation: 在绝缘基板上形成的集成电路半导体器件之间形成导电互连区域的工艺利用半导体材料本身形成器件互连区域。 半导体材料的图案层直接形成在绝缘基板的表面上。 图案化层包括要形成半导体器件的区域以及用于互连预定半导体器件的端子的区域。 在半导体材料的选定区域中形成半导体器件之后，图案化成互连的半导体材料的区域被转换为半导体材料的金属化合物。

公开(公告)号：US5547883A

公开(公告)日：1996-08-20

申请号：US504688

申请日：1995-07-20

Applicant: In Kim

Inventor： In Kim

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786 ,  H01L21/86

CPC classification number: H01L29/78696 ,  H01L21/84 ,  H01L29/42384 ,  H01L29/66765 ,  H01L29/78624 ,  H01L29/78642 ,  Y10S148/15

Abstract: A thin film transistor having increased channel length and self-aligned source and drain regions is fabricated by forming a gate electrode on an insulation film disposed on a substrate. Portions of the insulation film are then etched on opposite sides of the gate electrode, as well as beneath part of the gate electrode. A gate insulation film is then formed on the entire exposed surface of the gate electrode, and a semiconductor layer is then formed on the entire gate insulation film, as well as portions of the insulation film. Doping impurities may then be implanted at an angle other than 90.degree. to the surface of the substrate to achieve a thin film transistor having an extended channel length but occupying a relatively small area on the surface of the substrate.

Abstract translation: 通过在设置在基板上的绝缘膜上形成栅电极来制造具有增加的沟道长度和自对准源极和漏极区的薄膜晶体管。 然后在栅电极的相对侧以及栅电极的下方蚀刻绝缘膜的一部分。 然后在栅电极的整个暴露表面上形成栅极绝缘膜，然后在整个栅极绝缘膜上形成半导体层以及绝缘膜的一部分。 然后可以以与基板表面90度以外的角度注入掺杂杂质，以实现具有延伸的沟道长度但占据基板表面上较小面积的薄膜晶体管。

公开(公告)号：US5512501A

公开(公告)日：1996-04-30

申请号：US342024

申请日：1994-11-16

Applicant: Hideto Hidaka ,  Takahiro Tsuruda ,  Katsuhiro Suma

Inventor： Hideto Hidaka ,  Takahiro Tsuruda ,  Katsuhiro Suma

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L29/786 ,  H01L21/86

CPC classification number: H01L27/10873 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/11 ,  Y10S148/15

Abstract: In etching a polysilicon layer above a gate electrode layer, a portion of the gate electrode layer is left thereunder. The etching process of that polysilicon layer and that gate electrode layer is carried out in two steps of etching the polysilicon layer and an interlayer insulating layer, and etching the gate electrode layer and the gate oxide film. Therefore, the amount that is removed from an SOI layer can be suppressed in the manufacturing process thereof.

Abstract translation: 在蚀刻栅电极层上方的多晶硅层之后，栅电极层的一部分留在其下。 该多晶硅层和该栅电极层的蚀刻工艺是在蚀刻多晶硅层和层间绝缘层的两个步骤中进行，蚀刻栅电极层和栅极氧化膜。 因此，能够抑制从SOI层除去的量。

公开(公告)号：US5466618A

公开(公告)日：1995-11-14

申请号：US366224

申请日：1994-12-29

Applicant: Jin H. Kim

Inventor： Jin H. Kim

IPC: H01L21/86 ,  H01L21/786

CPC classification number: H01L21/86

Abstract: A method for fabricating an LCD-TFT, which can prevent degradation of image quality of a liquid crystal display by preventing blackening of the pixel electrode due to H.sub.2 plasma at the time of deposition of a protective insulation film. The method includes the steps of forming a gate electrode on a transparent glass substrate, and forming a gate insulation film, a semiconductor layer, and an impurity doped semiconductor layer successively over the surface of the substrate. The semiconductor layer and the impurity doped semiconductor layer are patterned, leaving layers only over a part of the gate insulation film over the gate electrode. A pixel electrode is formed on a part of the gate insulation film offset from the gate electrode. A metal barrier layer and source/drain electrodes are over the surface of the substrate. The metal barrier layer and the source/drain electrodes are patterned so as to expose the impurity doped semiconductor layer over the gate electrode and to cover all the surface of the pixel electrode. The semiconductor layer under the impurity doped semiconductor layer is exposed by carrying out a selective etching of the exposed impurity doped semiconductor layer with the metal barrier layer and the source/drain electrodes used as masks. A protective insulation layer is formed over the surface of the substrate, and the pixel electrode is exposed by selectively removing the protective insulation layer, the metal barrier layer and the source/drain electrodes over the pixel electrode.

Abstract translation: 一种用于制造LCD-TFT的方法，其可以通过防止在保护绝缘膜沉积时由于H 2等离子体而引起的像素电极的黑化而防止液晶显示器的图像质量的劣化。 该方法包括以下步骤：在透明玻璃基板上形成栅电极，并在衬底的表面上依次形成栅极绝缘膜，半导体层和杂质掺杂半导体层。 对半导体层和杂质掺杂半导体层进行图案化，仅在栅电极上的栅绝缘膜的一部分上留下层。 像素电极形成在偏离栅电极的栅极绝缘膜的一部分上。 金属阻挡层和源/漏电极在衬底的表面上方。 图案化金属阻挡层和源/漏电极，以便在栅极上暴露杂质掺杂半导体层并覆盖像素电极的所有表面。 通过对金属阻挡层和用作掩模的源极/漏极进行暴露的杂质掺杂半导体层的选择性蚀刻来暴露杂质掺杂半导体层下的半导体层。 在基板的表面上形成保护绝缘层，通过选择性地去除像素电极上的保护绝缘层，金属阻挡层和源极/漏极，露出像素电极。

公开(公告)号：US5233211A

公开(公告)日：1993-08-03

申请号：US771756

申请日：1991-10-04

Applicant: Yutaka Hayashi ,  Masaaki Kamiya ,  Yoshikazu Kojima ,  Hiroaki Takasu

Inventor： Yutaka Hayashi ,  Masaaki Kamiya ,  Yoshikazu Kojima ,  Hiroaki Takasu

IPC: G02F1/136 ,  G02F1/1335 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L21/86 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC classification number: G02F1/13454 ,  G02F1/136209 ,  G02F1/1368 ,  H01L21/84 ,  H01L21/86 ,  H01L27/1203 ,  H01L27/1214 ,  H01L29/66772 ,  H01L29/78633 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78654 ,  G02F1/133512 ,  G02F2001/13613 ,  G02F2202/105 ,  Y10S148/012 ,  Y10S148/15 ,  Y10S438/977

Abstract: The invention provides a semi-conductor light valve device and a process for fabricating the same. The device comprises a composite substrate having a supporte substrate, a light-shielding thin film formed on said supporte substrate and semiconductive thin film disposed on the light-shielding thin film with interposing an insulating thin film. A switching element made of a transistor and a transparent electrode for driving light valve are formed on the semiconductive thin film, and the switching element and the transparent electrode are connected electrically with each other. The transistor includes a channel region in the semiconductive thin film and a main gate electrode for controlling the conduction in the channel region, and the light-shielding thin film layer is so formed as to cover the channel region on the side opposite to said channel region, so as to prevent effectively a back channel and shut off the incident light.

公开(公告)号：US5100810A

公开(公告)日：1992-03-31

申请号：US738443

申请日：1991-07-31

Applicant: Makoto Yoshimi ,  Minoru Takahashi

Inventor： Makoto Yoshimi ,  Minoru Takahashi

IPC: H01L21/331 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L21/86 ,  H01L27/06 ,  H01L27/12 ,  H01L29/165 ,  H01L29/73 ,  H01L29/786

CPC classification number: H01L29/66265 ,  H01L21/76248 ,  H01L21/76264 ,  H01L21/764 ,  H01L21/8249 ,  H01L21/86 ,  H01L29/7317 ,  H01L29/78621 ,  H01L21/76272 ,  H01L21/76289 ,  Y10S148/15

Abstract: On the surface of an insulating substrate, a semi-conductor layer composed of a semiconductor layer of a first conductivity type on which a high-concentration semiconductor layer of the first conductivity type is formed. By selectively etching the semiconductor layer, the high-concentration external base region of the first conductivity is left, and at the same time, only a thicker prospective internal base region just under the external base region and a prospective emitter region and prospective collector region, which are located on both sides of the prospective internal base region and have steps between themselves and the prospective internal base region, are left to form island regions. A sidewall insulating film is formed which covers at least the sidewalls on the prospective collector region side among sidewalls of the external base region and sidewalls at the steps of the prospective internal base region adjoining the sidewalls of the external base region. The emitter region and collector region of the second conductivity type are formed by ion implantation perpendicular to the substrate with the insulating film covering the external base region and the sidewall insulating film as blocking mask.

Abstract translation: 在绝缘基板的表面上，形成由第一导电类型的半导体层构成的半导体层，其上形成有第一导电类型的高浓度半导体层。 通过选择性地蚀刻半导体层，留下第一导电性的高浓度外部基极区域，同时仅在外部基极区域正下方较厚的预期内部基极区域和预期的发射极区域和预期的集电极区域， 位于前瞻性内部基础地区两侧，并在自己与前瞻性内部基地区之间形成一个台阶，留在岛屿地区。 形成侧壁绝缘膜，该侧壁绝缘膜至少覆盖外部基极区域的侧壁中的前瞻性集电极区域侧的侧壁和邻接外部基极区域的侧壁的预期内部基极区域的侧壁。 通过垂直于衬底的离子注入形成第二导电类型的发射极区域和集电极区域，其中绝缘膜覆盖外部基极区域和侧壁绝缘膜作为阻挡掩模。

公开(公告)号：US5066613A

公开(公告)日：1991-11-19

申请号：US380175

申请日：1989-07-13

Applicant: Ronald E. Reedy ,  Graham A. Garcia ,  Isaac Lagnado

Inventor： Ronald E. Reedy ,  Graham A. Garcia ,  Isaac Lagnado

IPC: H01L21/768 ,  H01L21/86 ,  H01L23/482

CPC classification number: H01L23/4825 ,  H01L21/76889 ,  H01L21/86 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/147

Abstract: A process for developing conductive interconnect regions between integrated circuit semiconductor devices formed on an insulating substrate utilizes the semiconductor material itself for formation of device interconnect regions.A patterned layer of semiconductor material is formed directly on the surface of an insulating substrate. The patterned layer includes regions where semiconductor devices are to be formed and regions which are to be used to interconnect terminals of predetermined ones of the semiconductor devices. After forming the semiconductor devices in selected regions of the semiconductor material, the regions of the semiconductor material patterned for becoming interconnects are converted to a metallic compound of the semiconductor material.

Abstract translation: 在绝缘基板上形成的集成电路半导体器件之间形成导电互连区域的工艺利用半导体材料本身形成器件互连区域。 半导体材料的图案层直接形成在绝缘基板的表面上。 图案化层包括要形成半导体器件的区域以及用于互连预定半导体器件的端子的区域。 在半导体材料的选定区域中形成半导体器件之后，图案化成互连的半导体材料的区域被转换为半导体材料的金属化合物。

公开(公告)号：US5037774A

公开(公告)日：1991-08-06

申请号：US73839

申请日：1987-07-15

Applicant: Hideki Yamawaki ,  Yoshihiro Arimoto ,  Shigeo Kodama ,  Takafumi Kimura ,  Masaru Ihara

Inventor： Hideki Yamawaki ,  Yoshihiro Arimoto ,  Shigeo Kodama ,  Takafumi Kimura ,  Masaru Ihara

IPC: H01L27/12 ,  H01L21/20 ,  H01L21/205 ,  H01L21/324 ,  H01L21/86

CPC classification number: H01L21/324 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0262 ,  Y10S148/017 ,  Y10S148/025 ,  Y10S148/15

Abstract: Process for the production of semiconductor devices by using silicon-on-insulator (SOI) techniques. The Si layers of the SOI structure include an interfacial layer of Si and a buffer layer of Si formed thereon, whereby the formation of stacking faults in the Si layers can be effectively prevented. Pretreatment of the underlying insulating material with a molybdate solution and interposition of an additional layer of slowly grown single-crystalline Si between the buffer layer of Si and the overlying active Si layer are also effective to inhibit the stacking faults. Semiconductor devices with high quality can be produced with good yield.

Abstract translation: 通过使用绝缘体上硅（SOI）技术制造半导体器件的工艺。 SOI结构的Si层包括Si的界面层和在其上形成的Si的缓冲层，由此可以有效地防止在Si层中形成堆垛层错。 用钼酸盐溶液预处理下层绝缘材料，并在Si的缓冲层和上覆的有源Si层之间插入缓慢生长的单晶Si的附加层也有效地抑制堆垛层错。 可以以良好的产量生产具有高质量的半导体器件。

公开(公告)号：US4693758A

公开(公告)日：1987-09-15

申请号：US784033

申请日：1985-10-04

Applicant: Yutaka Kobayashi ,  Takaya Suzuki

Inventor： Yutaka Kobayashi ,  Takaya Suzuki

IPC: H01L29/78 ,  H01L21/20 ,  H01L21/205 ,  H01L21/26 ,  H01L21/268 ,  H01L21/428 ,  H01L21/86 ,  H01L27/12 ,  H01L29/786 ,  H01L21/263 ,  H01L21/225

CPC classification number: H01L27/12 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02686 ,  H01L21/268 ,  H01L29/78657 ,  Y10S117/904 ,  Y10S438/967

Abstract: This invention relates to improvements in the SOS technology including the so-called laser annealing processing. According to this invention, a semiconductor layer of an SOS structure consists of the three layers of an interface layer made up of twins, a seed crystalline layer and a re-grown layer far thicker than the preceding two layers when viewed from the side of an insulating substrate. The re-grown layer is formed in such a way that a semiconductor layer deposited on the insulating substrate is irradiated with an electromagnetic wave, for example, pulsed ruby laser beam, which is absorbed substantially uniformly by a portion except the interface layer and the seed crystalline layer. According to this invention, the quality of the re-grown layer is improved, and the mobility of carriers is enhanced. As a result, the operating speed of a semiconductor device employing the SOS structure is raised, and the leakage current is reduced.

Abstract translation: 本发明涉及SOS技术的改进，包括所谓的激光退火处理。 根据本发明，SOS结构的半导体层由三层由双胞胎组成的界面层，晶种层和再生长层组成，当从 绝缘基板。 再生长层以这样的方式形成，使得沉积在绝缘基板上的半导体层被电磁波照射，例如脉冲红宝石激光束，其被除了界面层和种子之外的部分基本均匀地吸收 晶体层。 根据本发明，再生层的质量得到改善，并且载体的迁移率增强。 结果，使用SOS结构的半导体器件的工作速度提高，并且泄漏电流降低。