公开(公告)号：US5100810A

公开(公告)日：1992-03-31

申请号：US738443

申请日：1991-07-31

Applicant: Makoto Yoshimi ,  Minoru Takahashi

Inventor： Makoto Yoshimi ,  Minoru Takahashi

IPC: H01L21/331 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L21/86 ,  H01L27/06 ,  H01L27/12 ,  H01L29/165 ,  H01L29/73 ,  H01L29/786

CPC classification number: H01L29/66265 ,  H01L21/76248 ,  H01L21/76264 ,  H01L21/764 ,  H01L21/8249 ,  H01L21/86 ,  H01L29/7317 ,  H01L29/78621 ,  H01L21/76272 ,  H01L21/76289 ,  Y10S148/15

Abstract: On the surface of an insulating substrate, a semi-conductor layer composed of a semiconductor layer of a first conductivity type on which a high-concentration semiconductor layer of the first conductivity type is formed. By selectively etching the semiconductor layer, the high-concentration external base region of the first conductivity is left, and at the same time, only a thicker prospective internal base region just under the external base region and a prospective emitter region and prospective collector region, which are located on both sides of the prospective internal base region and have steps between themselves and the prospective internal base region, are left to form island regions. A sidewall insulating film is formed which covers at least the sidewalls on the prospective collector region side among sidewalls of the external base region and sidewalls at the steps of the prospective internal base region adjoining the sidewalls of the external base region. The emitter region and collector region of the second conductivity type are formed by ion implantation perpendicular to the substrate with the insulating film covering the external base region and the sidewall insulating film as blocking mask.

Abstract translation: 在绝缘基板的表面上，形成由第一导电类型的半导体层构成的半导体层，其上形成有第一导电类型的高浓度半导体层。 通过选择性地蚀刻半导体层，留下第一导电性的高浓度外部基极区域，同时仅在外部基极区域正下方较厚的预期内部基极区域和预期的发射极区域和预期的集电极区域， 位于前瞻性内部基础地区两侧，并在自己与前瞻性内部基地区之间形成一个台阶，留在岛屿地区。 形成侧壁绝缘膜，该侧壁绝缘膜至少覆盖外部基极区域的侧壁中的前瞻性集电极区域侧的侧壁和邻接外部基极区域的侧壁的预期内部基极区域的侧壁。 通过垂直于衬底的离子注入形成第二导电类型的发射极区域和集电极区域，其中绝缘膜覆盖外部基极区域和侧壁绝缘膜作为阻挡掩模。

公开(公告)号：US5485028A

公开(公告)日：1996-01-16

申请号：US38946

申请日：1993-03-29

Applicant: Minoru Takahashi ,  Makoto Yoshimi ,  Naoyuki Shigyo

Inventor： Minoru Takahashi ,  Makoto Yoshimi ,  Naoyuki Shigyo

IPC: H01L21/336 ,  H01L29/786 ,  H01L27/01 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L29/78696 ,  H01L29/66772

Abstract: In a semiconductor device having a thin SOI film, the thickness of a semiconductor layer formed on an insulating film is so adjusted as to be less than a maximum distance allowable to complete depletion of the layer. While the thickness of a channel region is adjusted to be less than that of impurity-diffusion regions. Further, the insulating layer is so formed to have a thicker portion under the channel region, and thinner portions under the source region and the drain region as the impurity-diffusion regions. The semiconductor layer has steps at the boundaries between the channel region and the impurity-diffusion regions, and the top face of the channel region is arranged so as to be lower than the top faces of the impurity-diffusion regions. A region having a width less than the maximum depletion distance and an impurity concentration larger, than that of the channel region and less than that of the drain region is formed between the channel region and the drain region.

Abstract translation: 在具有薄SOI膜的半导体器件中，形成在绝缘膜上的半导体层的厚度被调整为小于可以完全消耗该层的最大距离。 而通道区域的厚度被调整为小于杂质扩散区域的厚度。 此外，绝缘层被形成为在沟道区下方具有较厚部分，并且在作为杂质扩散区的源极区和漏极区下方具有较薄部分。 半导体层在沟道区域和杂质扩散区域之间的边界处具有台阶，并且沟道区域的顶面被布置成低于杂质扩散区域的顶面。 在沟道区域和漏极区域之间形成具有小于最大耗尽距离的宽度和杂质浓度大于沟道区域且小于漏极区域的区域的区域。

公开(公告)号：US5895956A

公开(公告)日：1999-04-20

申请号：US569844

申请日：1995-12-08

Applicant: Yukihito Oowaki ,  Masako Yoshida ,  Makoto Yoshimi

Inventor： Yukihito Oowaki ,  Masako Yoshida ,  Makoto Yoshimi

IPC: H01L21/8242 ,  G11C11/4091 ,  H01L27/108 ,  H01L27/12 ,  H01L29/76 ,  H01L29/786 ,  H01L27/01

CPC classification number: G11C11/4091 ,  H01L27/10897 ,  H01L27/12

Abstract: A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.

公开(公告)号：US20100193900A1

公开(公告)日：2010-08-05

申请号：US12667623

申请日：2008-02-25

Applicant: Tadahiro Ohmi ,  Akinobu Teramoto ,  Sumio Sano ,  Makoto Yoshimi

Inventor： Tadahiro Ohmi ,  Akinobu Teramoto ,  Sumio Sano ,  Makoto Yoshimi

IPC: H01L27/12 ,  H01L21/762

CPC classification number: H01L21/76254 ,  H01L27/1203

Abstract: A base is formed of a material, such as SiC, having mechanical characteristics higher than those of silicon for forming a semiconductor layer, and the base and the semiconductor layer are bonded through an insulating layer. After bonding, an SOI substrate is formed by mechanically separating the semiconductor layer from the base, and the separated semiconductor layer is reused for forming the subsequent SOI substrate. Thus, a large SOI substrate having a diameter of 400 mm or more, which has been difficult to obtain by conventional methods, can be obtained.

Abstract translation: 基体由诸如SiC的材料形成，具有比用于形成半导体层的硅的机械特性更高的机械特性，并且基底和半导体层通过绝缘层接合。 在接合之后，通过将半导体层与基底机械分离来形成SOI衬底，并且将分离的半导体层重新用于形成随后的SOI衬底。 因此，可以获得通过常规方法难以获得的直径为400mm以上的大型SOI衬底。

公开(公告)号：US06376897B2

公开(公告)日：2002-04-23

申请号：US09314114

申请日：1999-05-19

Applicant: Takashi Yamada ,  Hideaki Nii ,  Makoto Yoshimi ,  Tomoaki Shino ,  Kazumi Inoh ,  Shigeru Kawanaka ,  Tsuneaki Fuse ,  Sadayuki Yoshitomi

Inventor： Takashi Yamada ,  Hideaki Nii ,  Makoto Yoshimi ,  Tomoaki Shino ,  Kazumi Inoh ,  Shigeru Kawanaka ,  Tsuneaki Fuse ,  Sadayuki Yoshitomi

IPC: H01L2900

CPC classification number: H01L29/1008 ,  H01L29/7317

Abstract: In a bipolar transistor improved to exhibit an excellent high-frequency property by decreasing the width of the intrinsic base with without increasing the base resistance, an emitter region, intrinsic base region and collector region are closely aligned on an insulating layer, and the intrinsic base region and the collector region make a protrusion projecting upward from the substrate surface. The protrusion has a width wider than the width of the intrinsic base region.

Abstract translation: 在通过在不增加基极电阻的情况下减小本征基极的宽度而改善为显示优异的高频特性的双极晶体管中，发射极区域，本征基极区域和集电极区域在绝缘层上紧密对准，并且本征基极 区域和集电区域形成从基板表面向上突出的突起。 突起的宽度比本征基区宽度宽。

公开(公告)号：US20070121150A1

公开(公告)日：2007-05-31

申请号：US11528263

申请日：2006-09-28

Applicant: Tetsuya Kobayashi ,  Takao Maekawa ,  Makoto Yoshimi ,  Kyoko Matsushita

Inventor： Tetsuya Kobayashi ,  Takao Maekawa ,  Makoto Yoshimi ,  Kyoko Matsushita

IPC: G06F3/12

CPC classification number: H04N1/32106 ,  H04N2201/0094 ,  H04N2201/3202 ,  H04N2201/3273

Abstract: A document processing apparatus performs plural types of processings for a document. The apparatus includes a control unit and a storage unit. The control unit receives an instruction group including a plurality of instructions of performing respective processings for a certain document. The storage unit stores: (i) plural pieces of individual processing result information indicating results of the plurality of processings for the certain document, respectively; and (ii) overall processing result information indicating a result of the overall instruction group.

Abstract translation: 文件处理装置对文档执行多种处理。 该装置包括控制单元和存储单元。 控制单元接收包括针对特定文档执行各个处理的多个指令的指令组。 存储单元存储：（i）分别指示该特定文档的多个处理的结果的多个个体处理结果信息; 和（ii）指示整个指令组的结果的整体处理结果信息。

公开(公告)号：US06174779B1

公开(公告)日：2001-01-16

申请号：US09267775

申请日：1999-03-15

Applicant: Tomoaki Shino ,  Takashi Yamada ,  Makoto Yoshimi ,  Shigeru Kawanaka ,  Hideaki Nii ,  Kazumi Inoh ,  Tsuneaki Fuse ,  Sadayuki Yoshitomi ,  Mamoru Terauchi

Inventor： Tomoaki Shino ,  Takashi Yamada ,  Makoto Yoshimi ,  Shigeru Kawanaka ,  Hideaki Nii ,  Kazumi Inoh ,  Tsuneaki Fuse ,  Sadayuki Yoshitomi ,  Mamoru Terauchi

IPC: H01L218228

CPC classification number: H01L29/66265 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7317

Abstract: In a lateral bipolar transistor, its emitter region, base region, link base region, and so forth, are made in self alignment with side walls of masks by using partly overlapping two mask patterns. Therefore, not relying on the mask alignment accuracy, these regions are made in a precisely controlled positional relation. Thus, the lateral bipolar transistor, thus obtained, is reduced in parasitic resistance of the base and parasitic junction capacitance between the emitter and the base, and alleviated in variance of characteristics caused by fluctuation of the length of a link base region, length of the emitter-base junction and relative positions of the emitter and the collector, and can be manufactured with a high reproducibility.

Abstract translation: 在横向双极晶体管中，通过使用部分重叠的两个掩模图案，其发射极区域，基极区域，链路基极区域等与掩模的侧壁自对准。 因此，不依赖于掩模对准精度，这些区域被精确控制位置关系。 因此，如此获得的横向双极晶体管的基极的寄生电阻和发射极与基极之间的寄生结电容减小，并且由于链路基极区域的长度的波动引起的特性的变化减轻， 发射极 - 基极结和发射极和集电极的相对位置，并且可以以高再现性制造。

公开(公告)号：US5886385A

公开(公告)日：1999-03-23

申请号：US914752

申请日：1997-08-20

Applicant: Osamu Arisumi ,  Akira Nishiyama ,  Makoto Yoshimi

Inventor： Osamu Arisumi ,  Akira Nishiyama ,  Makoto Yoshimi

IPC: H01L21/8242 ,  H01L21/336 ,  H01L27/108 ,  H01L29/45 ,  H01L29/786 ,  H01L27/01 ,  H01L29/78

CPC classification number: H01L29/66772 ,  H01L29/458 ,  H01L29/78612 ,  H01L29/78618

Abstract: A semiconductor device comprises: a first semiconductor layer 6 having a first conductivity formed on a substrate having a surface of an insulating material 4; a source region 16a and a drain region 16b, which are formed on the first semiconductor layer so as to be separated from each other and which have a second conductivity different from the first conductivity; a channel region 6 formed on the first semiconductor layer between the source region and the drain region; a gate electrode 10 formed on the channel region a gate sidewall 14 of an insulating material formed on a side of the gate electrode; and a second semiconductor layer 18 having the first conductivity formed on at least the source region. This semiconductor device can effectively suppress the floating-body effect with a simple structure.

Abstract translation: 半导体器件包括：具有第一导电性的第一半导体层6，其形成在具有绝缘材料4的表面的基板上; 源极区域16a和漏极区域16b，其形成在第一半导体层上以彼此分离并且具有不同于第一导电性的第二导电性; 形成在源极区域和漏极区域之间的第一半导体层上的沟道区域6; 形成在形成在栅极侧的绝缘材料的栅极侧壁14的沟道区域上的栅电极10; 以及在至少源极区上形成具有第一导电性的第二半导体层18。 该半导体装置能够以简单的结构有效地抑制浮体效应。

公开(公告)号：US5698869A

公开(公告)日：1997-12-16

申请号：US527515

申请日：1995-09-13

Applicant: Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

Inventor： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

IPC: H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L31/072

CPC classification number: H01L29/66666 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78681

Abstract: A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.

Abstract translation: 提供半导体器件的结构及其制造方法，其中可以减小漏电流，同时改善诸如MOSFET，MOSSIT和MISFET的绝缘栅晶体管的漏极击穿电压，以及保持特性 可以提高诸如使用这些晶体管的DRAM作为开关晶体管的存储单元，并且还可以提高传输栅极中的栅极氧化膜的可靠性。 更具体地，在SOI.IG器件中的源极区域或漏极区域的内部形成诸如SixGe1-x，SixSn1-x，PbS的窄带隙半导体区域。 通过选择SOI膜中的窄带隙半导体区域的位置和/或摩尔分数，或者选择一种杂质元素来补偿由于窄带隙半导体区域引起的晶格失配，可以抑制晶体缺陷的产生 。 此外，即使产生晶体缺陷，也可以抑制晶体缺陷对晶体管的影响或漏电流等存储特性的结构。

公开(公告)号：US20050276263A1

公开(公告)日：2005-12-15

申请号：US10978969

申请日：2004-11-01

Applicant: Takahiro Suetsugu ,  Hiroshi Kinoshita ,  Makoto Yoshimi

Inventor： Takahiro Suetsugu ,  Hiroshi Kinoshita ,  Makoto Yoshimi

IPC: H04L12/707 ,  H04J1/16 ,  H04J3/14 ,  H04L1/00 ,  H04L12/26 ,  H04L12/28 ,  H04L12/801 ,  H04L12/891 ,  H04L12/911 ,  H04L12/56

CPC classification number: H04L47/10 ,  H04L45/24 ,  H04L45/745 ,  H04L47/125 ,  H04L2012/5624

Abstract: A data transmission device 10 serving as a traffic distribution control device is a device which, in order to distribute traffic across a plurality of physical ports composing a logical port for link aggregation, uses a hash function to calculate a hash value from a destination address and a source address of a receive packet, and determines a destination physical port. The traffic distribution control device includes a measuring unit 13 that measures an output flow rate of a packet outputted from each of the plurality of physical ports; a calculating unit 14 that calculates a flow rate ratio between the plurality of physical ports with respect to the measured output flow rates; and a first control unit 12 that feeds the calculated flow rate ratio back to a bandwidth distribution ratio between the plurality of physical ports to change numerical allocation of hash values for determining the destination physical port.

Abstract translation: 作为流量分配控制装置的数据发送装置10是为了在构成用于链路聚合的逻辑端口的多个物理端口上分配流量的装置，使用散列函数来计算来自目的地地址的哈希值， 接收分组的源地址，并确定目的物理端口。 交通流量控制装置包括测量单元13，其测量从多个物理端口中的每一个输出的分组的输出流量; 计算单元14，其根据测量的输出流量计算多个物理端口之间的流量比; 以及第一控制单元12，其将计算的流量比率反馈到多个物理端口之间的带宽分配比，以改变用于确定目的地物理端口的哈希值的数值分配。