公开(公告)号：US09349686B2

公开(公告)日：2016-05-24

申请号：US14206360

申请日：2014-03-12

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang ,  Niladri Mojumder ,  Mustafa Badaroglu

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/02167 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

Abstract translation: 系统和方法涉及一种集成电路，其包括由具有比铜的平均自由路径更低的示例性材料形成的减小的高度M1金属线，用于集成电路的片上电路元件的局部布线，其中降低的高度 M1金属线低于由铜形成的常规M1金属线的最小允许或允许的高度。 用于形成还原高度M1金属线的示例性材料包括钨（W），钼（Mo）和钌（Ru），其中这些示例性材料还具有比铜更低的电容和更低的RC延迟，同时提供高电迁移可靠性。

公开(公告)号：US09318564B2

公开(公告)日：2016-04-19

申请号：US14281710

申请日：2014-05-19

Applicant: QUALCOMM Incorporated

Inventor： Niladri Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: H01L29/76 ,  H01L29/40 ,  H01L29/161 ,  H01L27/02 ,  H01L27/11

CPC classification number: H01L29/401 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/161

Abstract: Methods and apparatus directed toward a high density static random access memory (SRAM) array having advanced metal patterning are provided. In an example, provided is a method for fabricating an SRAM. The method includes forming, using a self-aligning double patterning (SADP) technique, a plurality of substantially parallel first metal lines oriented in a first direction in a first layer. The method also includes etching the substantially parallel first metal lines, using a cut mask, in a second direction substantially perpendicular to the first direction, to separate the substantially parallel first metal lines into a plurality of islands having first respective sides that are aligned in the first direction and second respective sides that are aligned the second direction. The method also includes forming, in a second layer, a plurality of second metal lines oriented in the first direction.

Abstract translation: 提供了针对具有高级金属图案化的高密度静态随机存取存储器（SRAM）阵列的方法和装置。 在一个示例中，提供了一种用于制造SRAM的方法。 该方法包括使用自对准双图案化（SADP）技术形成在第一层中沿第一方向定向的多个基本平行的第一金属线。 该方法还包括在基本上垂直于第一方向的第二方向上使用切割掩模蚀刻基本平行的第一金属线，以将基本上平行的第一金属线分离成多个岛，该岛具有在第 第一方向和第二相对侧对准第二方向。 该方法还包括在第二层中形成沿第一方向定向的多个第二金属线。

公开(公告)号：US08969166B2

公开(公告)日：2015-03-03

申请号：US14156785

申请日：2014-01-16

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Choh fei Yeap ,  Ping Liu

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/66492 ,  H01L29/7833 ,  Y02D70/00

Abstract: An apparatus for selectively improving integrated circuit performance is provided. In an example, an integrated circuit is fabricated according to an integrated circuit layout. A critical portion of the integrated circuit layout determines a speed of the integrated circuit, where at least a part of the critical portion includes at least one of a halo implant region, lightly doped drain (LDD) implant region, and source drain extension (SDE) implant region. A marker layer comprises the part of the critical portion that includes the at least one of the halo implant region, the lightly doped drain (LDD) implant region, and the source drain extension (SDE) implant region, and includes at least one transistor formed therefrom.

Abstract translation: 提供了一种用于选择性地提高集成电路性能的装置。 在一个示例中，根据集成电路布局制造集成电路。 集成电路布局的关键部分确定集成电路的速度，其中临界部分的至少一部分包括光晕注入区域，轻掺杂漏极（LDD）注入区域和源极漏极延伸（SDE）中的至少一个 ）植入区域。 标记层包括关键部分的包括所述卤素注入区，轻掺杂漏极（LDD）注入区和源极漏极延伸（SDE）注入区）中的至少一个的部分，并且包括形成的至少一个晶体管 由此。

公开(公告)号：US20150036437A1

公开(公告)日：2015-02-05

申请号：US13957460

申请日：2013-08-02

Applicant: Qualcomm Incorporated

Inventor： Xia Li ,  Bin Yang ,  Zhongze Wang

IPC: G11C16/10 ,  H01L21/28 ,  H01L29/66

CPC classification number: G11C16/10 ,  G11C16/0433 ,  G11C16/14 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: An apparatus includes a storage transistor. The storage transistor includes a floating gate configured to store electrical charge and a control gate. The floating gate is coupled to the control gate via capacitive coupling. The floating gate and the control gate are metal. The apparatus also includes an access transistor coupled to the storage transistor. A gate of the access transistor is coupled to a word line. The storage transistor and the access transistor are serially coupled between a bit line and a source line.

Abstract translation: 一种装置包括存储晶体管。 存储晶体管包括被配置为存储电荷的浮动栅极和控制栅极。 浮动栅极通过电容耦合耦合到控制栅极。 浮动门和控制门是金属的。 该装置还包括耦合到存储晶体管的存取晶体管。 存取晶体管的栅极耦合到字线。 存储晶体管和存取晶体管串联耦合在位线和源极线之间。

公开(公告)号：US20140211546A1

公开(公告)日：2014-07-31

申请号：US13869110

申请日：2013-04-24

Applicant: Industry-Academic Cooperation Foundation, Yonsei University ,  QUALCOMM INCORPORATED

Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Bin Yang ,  Zhongze Wang ,  Choh fei Yeap

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C11/417 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1104 ,  Y10T29/41

Abstract: Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.

Abstract translation: 公开了具有读优选单元结构和写驱动器的静态随机存取存储器（SRAM）。 在一个实施例中，SRAM具有六个晶体管位单元。 读优选位单元通过提供两个反相器来实现，每个反相器具有上拉晶体管，下拉晶体管和通过栅极晶体管。 每个上拉晶体管与反馈回路相关联。 反馈环路改善了随机的静态噪声容限。 每个晶体管具有宽度和长度。 传输栅晶体管的长度增加。 下拉晶体管的宽度彼此相等，并且也等于通过栅极晶体管的宽度。 通过栅极和下拉晶体管的宽度也可以相对于现有设计而增加。 也可以使用写辅助电路来提高性能。