公开(公告)号：US5780341A

公开(公告)日：1998-07-14

申请号：US762212

申请日：1996-12-06

申请人： Seiki Ogura

发明人： Seiki Ogura

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/42324 ,  H01L29/7885

摘要： A method for fabricating an electrically programmable memory device which has efficiency of electron injection from the channel to floating gate is provided. A substrate is provided having source and drain region with a channel therebetween. A floating gate structure is formed over portions of the source and drain regions and the channel. The structure includes a dielectric layer and a conductor layer thereover. The channel under the floating gate has both horizontal and vertical components. After forming the vertical and horizontal components, an N- drain region is formed in self-alignment with the vertical channel step region's edge. The depth of the N- drain is greater than the source region.

摘要翻译： 提供一种制造电可编程存储器件的方法，其具有从通道到浮动栅极的电子注入的效率。 提供了具有在其间具有通道的源极和漏极区域的衬底。 在栅极和漏极区域和沟道的部分上形成浮栅结构。 该结构包括介电层和其上的导体层。 浮动门下的通道具有水平和垂直分量。 在形成垂直和水平分量之后，形成与垂直通道阶梯区域边缘自对准的N沟道区域。 N-漏极的深度大于源极区域。

公开(公告)号：US5681770A

公开(公告)日：1997-10-28

申请号：US645726

申请日：1996-05-14

申请人： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

发明人： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265

CPC分类号： H01L27/11521 ,  H01L27/115 ,  Y10S438/972

摘要： A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells. Programming may be implemented with channel hot-electron tunneling using relatively low programming voltages thereby realizing faster programming time and closer bit-line spacing.

公开(公告)号：US5672892A

公开(公告)日：1997-09-30

申请号：US645827

申请日：1996-05-14

申请人： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

发明人： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  Y10S438/972

摘要： A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells. Programming may be implemented with channel hot-electron tunneling using relatively low programming voltages thereby realizing faster programming time and closer bit-line spacing.

摘要翻译： 一种用于制造高密度存储器阵列的方法。 将N型杂质注入p型衬底中以形成具有基本平坦轮廓的连续扩散轨道。 每个扩散轨定义相应的位线。 每个轨道限定与位线相关联的每对相邻存储器阵列单元的源极和漏极区域。 在一个实施例中，利用多层多晶硅来形成控制栅极，浮置栅极，源极和漏极。 在另一实施例中，利用多层多晶硅来形成辅助栅极，浮栅，源极和漏极。 在两个实施例中，多晶硅层自对准以显着减少多晶硅层重叠，从而使寄生电容最小化。 Domino和Skippy Domino方案用于对内存阵列单元进行编程和读取。 通过使用相对较低的编程电压的通道热电子隧穿可以实现编程，从而实现更快的编程时间和更靠近的位线间隔。

公开(公告)号：US5622881A

公开(公告)日：1997-04-22

申请号：US319393

申请日：1994-10-06

申请人： Joyce E. Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

发明人： Joyce E. Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S148/117 ,  Y10S438/981

摘要： Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

摘要翻译： 通过将浮置栅极结构限制在被薄氮化物层覆盖的隔离结构之间，可在电可编程存储器中实现提高的封装密度以及改进的性能和制造产量。 浮栅的限制是通过平面化，优选采用自限制化学/机械抛光工艺，覆盖覆盖隔离结构的氮化物层的表面来实现的。 然后可以在基本平坦的表面上形成栅极氧化物和控制电极连接，而不会损害器件必须承受编程的栅极氧化物的质量或击穿电压。 由于避免了形成这些连接的严格的拓扑结构，所以可能包括可能包括金属连接的低电阻连接的形成得到改进，并且允许将存储器单元的晶体管缩放到先前不可能的尺寸。

公开(公告)号：US5516726A

公开(公告)日：1996-05-14

申请号：US343150

申请日：1994-11-22

申请人： Paul S. Kim ,  Seiki Ogura

发明人： Paul S. Kim ,  Seiki Ogura

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L21/283

CPC分类号： H01L21/76895

摘要： A process, compatible with bipolar and CMOS processes, for making local interconnection of adjacent devices on a semiconductor substrate is disclosed. An electrically insulating etch stop layer is deposited over the semiconductor substrate including the device contact openings. A conductive layer is deposited over the etch stop layer. The conductive layer is patterned into a local interconnect by use of resist patterning and subtractive etching, stopping on the etch stop layer. By thermal activation, the conductive pattern and the underlying insulating material interact to become a single electrically conductive layer. This layer also establishes electrical contact to the devices thus completing the formation of the local interconnection of the devices on a semiconductor substrate.

摘要翻译： 公开了一种与双极和CMOS工艺兼容的工艺，用于在半导体衬底上进行相邻器件的局部互连。 电绝缘蚀刻停止层沉积在包括器件接触开口的半导体衬底上。 导电层沉积在蚀刻停止层上。 通过使用抗蚀剂图案化和减去蚀刻将导电层图案化成局部互连，停止在蚀刻停止层上。 通过热激活，导电图案和下面的绝缘材料相互作用成为单个导电层。 该层还建立与器件的电接触，从而完成半导体衬底上的器件的局部互连的形成。

公开(公告)号：US5516721A

公开(公告)日：1996-05-14

申请号：US393599

申请日：1995-02-23

申请人： Carol Galli ,  Louis L. Hsu ,  Seiki Ogura ,  Joseph F. Shepard

发明人： Carol Galli ,  Louis L. Hsu ,  Seiki Ogura ,  Joseph F. Shepard

IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L27/08 ,  H01L29/00

CPC分类号： H01L21/76224 ,  H01L21/02164 ,  H01L21/02282

摘要： A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. The structure can be readily and easily planarized, particularly if a polish-stop layer is applied over the body of semiconductor material and voids and contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on a resist used to form the trench.

摘要翻译： 浅沟槽隔离结构通过具有减少步数和热量预算的工艺形成，通过用绝缘半导体氧化物的液相沉积填充沟槽并热处理沉积物以在层间的界面处形成高质量的热氧化物层 沉积的氧化物和沟槽延伸到其中的半导体材料（例如衬底）的主体。 该方法产生具有减小的应力和降低电荷泄漏倾向的隔离结构。 该结构可以容易且容易地平坦化，特别是如果抛光停止层施加在半导体材料的主体上并且空隙和沉积的氧化物的污染基本上通过在孔的体积上的沟槽上的自对准沉积而被消除 抗蚀剂用于形成沟槽。

公开(公告)号：US5384277A

公开(公告)日：1995-01-24

申请号：US169875

申请日：1993-12-17

申请人： Louis L. Hsu ,  Toshio Mii ,  Joseph F. Shepard ,  Seiki Ogura

发明人： Louis L. Hsu ,  Toshio Mii ,  Joseph F. Shepard ,  Seiki Ogura

IPC分类号： H01L21/285 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L21/28525 ,  H01L27/10829

摘要： A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain combine with nitride sidewalls on a gate contact aperture to separate a gate contact from source and drain contacts.

摘要翻译： 一种形成具有沟槽电容器的MOS DRAM单元的方法，其中与沟槽电容器的带连接，源极，漏极和隔离都在单晶硅的表面上方升高，包括以下步骤：形成沟槽电容器， 包括栅极氧化物和一组栅极层的覆盖栅极堆叠，然后使用栅极氧化物作为蚀刻停止层，在隔离栅堆叠中蚀刻的孔中沉积隔离元件。 用于形成LDD源极和漏极的相同侧壁与栅极接触孔上的氮化物侧壁结合，以将栅极接触与源极和漏极接触分开。

公开(公告)号：US5334281A

公开(公告)日：1994-08-02

申请号：US876598

申请日：1992-04-30

申请人： George W. Doerre ,  Seiki Ogura ,  Nivo Rovedo

发明人： George W. Doerre ,  Seiki Ogura ,  Nivo Rovedo

IPC分类号： H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L21/08

CPC分类号： H01L21/76251 ,  H01L21/31053 ,  H01L21/32105 ,  Y10S148/05 ,  Y10S438/97

摘要： An SOI wafer has a device layer of initial thickness that is formed into a set of mesas in the interval between which a temporary layer of polysilicon is deposited to a precisely controlled thickness. This polysilicon is entirely converted in a self-limiting process to an oxide etch stop having a thickness much smaller than the initial thickness. The mesas are thinned by a chemical mechanical polishing technique until the mesa is the same level as the top surface of the new oxide. The etch stop layer of oxide is not removed but serves both as an isolating layer to provide dielectric isolation between mesas in the final circuit and also as a visual gauge to determine the time when the polishing process should stop.

摘要翻译： SOI晶片具有初始厚度的器件层，其在其间沉积有临时多晶硅层的区域中形成一组台面，以精确控制的厚度。 该多晶硅在自限制过程中被完全转换成具有远小于初始厚度的厚度的氧化物蚀刻停止。 通过化学机械抛光技术使台面变薄，直到台面与新氧化物的顶表面相同。 氧化物的蚀刻停止层不被去除，而是用作隔离层，以在最终电路中的台面之间提供介电隔离，并且还用作可视仪器以确定抛光过程应该停止的时间。

公开(公告)号：US5120668A

公开(公告)日：1992-06-09

申请号：US727992

申请日：1991-07-10

申请人： Louis L. Hsu ,  Seiki Ogura ,  Joseph F. Shepard ,  Paul J. Tsang

发明人： Louis L. Hsu ,  Seiki Ogura ,  Joseph F. Shepard ,  Paul J. Tsang

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/66606 ,  H01L29/42376 ,  H01L29/7836

摘要： A method of forming an LDD field effect transistor with an inverted "T"-gate structure in which consecutive, conformal layers of polysilicon, metal and nitride or oxide are deposited to fill the recess in a composite interconnect layer on top of a trench isolated region of a semiconductor substrate. These conformal layers successively decrease in thickness and are selectively etched in two steps to form a self-aligned inverted T structure. A first reactive ion etch (RIE) step preferentially etches the exposed outer polysilicon to a certain depth. During a second step RIE the polysilicon layer is completely etched down to the a gate oxide surface and the metal layer is preferentially etched so that subtends only the remaining nitride or oxide cap.

公开(公告)号：US4982257A

公开(公告)日：1991-01-01

申请号：US452450

申请日：1989-12-19

申请人： Shah Akbar ,  Patricia L. Kroesen ,  Seiki Ogura ,  Nivo Rovedo

发明人： Shah Akbar ,  Patricia L. Kroesen ,  Seiki Ogura ,  Nivo Rovedo

IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/732

摘要： A compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer; a base layer disposed over the collector layer; an emitter layer disposed over the base layer; a first sidewall insulating layer disposed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with an extending laterally from another side of the base layer. The structure further includes a base contact interconnect disposed on a surface of the base contact extension layer and; a collector contact extension layer formed from doped semiconductor material with the same conductivity type as the collector layer, with the collector contact extension layer being in contact with the collector layer and extending laterally from or below the one side thereof; and a collector contact interconnect disposed on a surface of the collector contact extension layer and separated from said emitter layer by only one or more insulating layers.

摘要翻译： 压缩的垂直双极晶体管配置，消除了标准对称基极接触的一侧，同时也消除了对集电极触点的要求。 双极晶体管包括：集电极层; 设置在所述集电极层上的基层; 设置在所述基底层上的发射极层; 邻近并与发射极层，基极层和集电极层的至少一部分接触的第一侧壁绝缘层; 第二侧壁绝缘层，邻近并与发射极层的另一侧接触并且与基底层的至少一部分接触; 以及由与所述基底层相同导电类型的重掺杂半导体材料形成的基底接触延伸层，所述基底接触延伸层与从所述基底层的另一侧横向延伸接触。 所述结构还包括设置在所述基部接触延伸层的表面上的基极接触互连; 集电极接触延伸层，其由与所述集电体层相同的导电类型的掺杂半导体材料形成，所述集电极接触延伸层与所述集电极层接触并从其一侧或下方延伸; 以及集电极触点互连，其设置在集电极接触延伸层的表面上，并且仅通过一个或多个绝缘层与所述发射极层分离。