公开(公告)号：US5541130A

公开(公告)日：1996-07-30

申请号：US477791

申请日：1995-06-07

Applicant: Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

Inventor： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L27/115 ,  Y10S438/972

Abstract: A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells. Programming may be implemented with channel hot-electron tunneling using relatively low programming voltages thereby realizing faster programming time and closer bit-line spacing.

Abstract translation: 一种用于制造高密度存储器阵列的方法。 将N型杂质注入p型衬底中以形成具有基本平坦轮廓的连续扩散轨道。 每个扩散轨定义相应的位线。 每个轨道限定与位线相关联的每对相邻存储器阵列单元的源极和漏极区域。 在一个实施例中，利用多层多晶硅来形成控制栅极，浮置栅极，源极和漏极。 在另一实施例中，利用多层多晶硅来形成辅助栅极，浮栅，源极和漏极。 在两个实施例中，多晶硅层自对准以显着减少多晶硅层重叠，从而使寄生电容最小化。 Domino和Skippy Domino方案用于对内存阵列单元进行编程和读取。 通过使用相对较低的编程电压的通道热电子隧穿可以实现编程，从而实现更快的编程时间和更靠近的位线间隔。

公开(公告)号：US5654917A

公开(公告)日：1997-08-05

申请号：US645680

申请日：1996-05-14

Applicant: Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

Inventor： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC classification number: H01L27/11521 ,  H01L27/115 ,  Y10S438/972

Abstract: A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells. Programming may be implemented with channel hot-electron tunneling using relatively low programming voltages thereby realizing faster programming time and closer bit-line spacing.

公开(公告)号：US5681770A

公开(公告)日：1997-10-28

申请号：US645726

申请日：1996-05-14

Applicant: Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

Inventor： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265

CPC classification number: H01L27/11521 ,  H01L27/115 ,  Y10S438/972

Abstract: A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells. Programming may be implemented with channel hot-electron tunneling using relatively low programming voltages thereby realizing faster programming time and closer bit-line spacing.

公开(公告)号：US5672892A

公开(公告)日：1997-09-30

申请号：US645827

申请日：1996-05-14

Applicant: Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

Inventor： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L27/115 ,  Y10S438/972

Abstract: A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells. Programming may be implemented with channel hot-electron tunneling using relatively low programming voltages thereby realizing faster programming time and closer bit-line spacing.

Abstract translation: 一种用于制造高密度存储器阵列的方法。 将N型杂质注入p型衬底中以形成具有基本平坦轮廓的连续扩散轨道。 每个扩散轨定义相应的位线。 每个轨道限定与位线相关联的每对相邻存储器阵列单元的源极和漏极区域。 在一个实施例中，利用多层多晶硅来形成控制栅极，浮置栅极，源极和漏极。 在另一实施例中，利用多层多晶硅来形成辅助栅极，浮栅，源极和漏极。 在两个实施例中，多晶硅层自对准以显着减少多晶硅层重叠，从而使寄生电容最小化。 Domino和Skippy Domino方案用于对内存阵列单元进行编程和读取。 通过使用相对较低的编程电压的通道热电子隧穿可以实现编程，从而实现更快的编程时间和更靠近的位线间隔。

公开(公告)号：US06256755B1

公开(公告)日：2001-07-03

申请号：US09174789

申请日：1998-10-19

Applicant: Terence B. Hook ,  Chung H. Lam ,  Eric S. Lee ,  James S. Nakos ,  Nivo Rovedo ,  Richard Q. Williams ,  Robert C. Wong

Inventor： Terence B. Hook ,  Chung H. Lam ,  Eric S. Lee ,  James S. Nakos ,  Nivo Rovedo ,  Richard Q. Williams ,  Robert C. Wong

IPC: G11C2900

CPC classification number: G11C16/349 ,  G11C16/04 ,  G11C16/3495 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012

Abstract: An apparatus and method for detecting a defective array of NVRAM cells. A counter is provided which times an erase time interval for the NVRAM cells during a regular erase function. The computed erase interval is compared with a maximum erase interval to determine at least a first characteristic which indicates the block of NVRAMs is at the end of its useful life. A second characteristic is determined by computing the slope in the erase time function versus the number of simulated erase functions. When the slope of the erase function exceeds a maximum slope, the NVRAM array is determined to be at the end of its useful life.

Abstract translation: 一种用于检测NVRAM单元的不良阵列的装置和方法。 在常规擦除功能期间提供计数器，其为NVRAM单元的擦除时间间隔。 计算的擦除间隔与最大擦除间隔进行比较，以确定至少第一特性，其指示NVRAM的块处于其使用寿命的结束。 通过计算擦除时间函数中的斜率与模拟擦除函数的数量来确定第二特性。 当擦除功能的斜率超过最大斜率时，NVRAM阵列被确定为其使用寿命结束。

公开(公告)号：US08035126B2

公开(公告)日：2011-10-11

申请号：US11926399

申请日：2007-10-29

Applicant: Phung T. Nguyen ,  Robert C. Wong

Inventor： Phung T. Nguyen ,  Robert C. Wong

IPC: H01L29/74

CPC classification number: H01L27/11 ,  G11C11/39 ,  H01L29/66659

Abstract: A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is electrically common to the emitter/collector of the FET and a base of the NPN of the PNPN device is electrically common to the channel region of the FET. The anode pin of the PNPN device may be used as a word line or a bit line. A method of forming the 1T SRAM device is also disclosed.

Abstract translation: 公开了一种单晶体管静态随机存取存储器（1T SRAM）器件和电路实现方式。 1T SRAM器件包括在单元表面上的平面场效应晶体管（FET）和集成在FET一侧的垂直PNPN器件。 PNPN器件的PNP的基极与FET的发射极/集电极电气公共，并且PNPN器件的NPN的基极与FET的沟道区域电气公共。 PNPN器件的阳极引脚可以用作字线或位线。 还公开了一种形成1T SRAM器件的方法。

公开(公告)号：US07781797B2

公开(公告)日：2010-08-24

申请号：US11427406

申请日：2006-06-29

Applicant: Phung T. Nguyen ,  Robert C. Wong

Inventor： Phung T. Nguyen ,  Robert C. Wong

IPC: H01L29/74

CPC classification number: H01L29/66659 ,  H01L27/1025 ,  H01L27/1027 ,  H01L27/11

Abstract: A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is electrically common to the emitter/collector of the FET and a base of the NPN of the PNPN device is electrically common to the channel region of the FET. The anode pin of the PNPN device may be used as a word line or a bit line. A method of forming the 1T SRAM device is also disclosed.

Abstract translation: 公开了一种单晶体管静态随机存取存储器（1T SRAM）器件和电路实现方式。 1T SRAM器件包括在单元表面上的平面场效应晶体管（FET）和集成在FET一侧的垂直PNPN器件。 PNPN器件的PNP的基极与FET的发射极/集电极电气公共，并且PNPN器件的NPN的基极与FET的沟道区域电气公共。 PNPN器件的阳极引脚可以用作字线或位线。 还公开了一种形成1T SRAM器件的方法。

公开(公告)号：US20090108356A1

公开(公告)日：2009-04-30

申请号：US11924053

申请日：2007-10-25

Applicant: Kangguo Cheng ,  Michael P. Chudzik ,  Rama Divakaruni ,  Geng Wang ,  Robert C. Wong ,  Haining S. Yang

Inventor： Kangguo Cheng ,  Michael P. Chudzik ,  Rama Divakaruni ,  Geng Wang ,  Robert C. Wong ,  Haining S. Yang

IPC: H01L29/78 ,  H01L21/44

CPC classification number: H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.

Abstract translation: 在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。 在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整 氧化层。 还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。 在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。

公开(公告)号：US20090026523A1

公开(公告)日：2009-01-29

申请号：US11782079

申请日：2007-07-24

Applicant: Robert C. Wong ,  Haining S. Yang

Inventor： Robert C. Wong ,  Haining S. Yang

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/66795 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1211 ,  H01L29/785

Abstract: A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the opposite side of the first sidewall is not controlled by the gate electrode. A partially gated finFET, that is, a finFET with a gate electrode on the first sidewall and without a gate electrode on the second sidewall is thus formed. Conventional dual gate finFETs may be formed with the inventive partially gated finFETs on the same substrate to provide multiple finFETs having different on-current in the same circuit such as an SRAM circuit.

Abstract translation: 在至少一个半导体鳍片的侧壁上形成栅极电介质和栅极导体层。 图案化栅极导体层，使得栅极电极形成在半导体鳍片的一部分的第一侧壁上，而在第一侧壁的相对侧上的第二侧壁不受栅电极控制。 因此，形成了部分选通的finFET，即在第一侧壁上具有栅电极且在第二侧壁上没有栅电极的finFET。 传统的双栅极finFET可以在同一衬底上与本发明的部分选通的鳍状FET形成，以在诸如SRAM电路的同一电路中提供具有不同导通电流的多个finFET。

公开(公告)号：US07355906B2

公开(公告)日：2008-04-08

申请号：US11420049

申请日：2006-05-24

Applicant: Rajiv V. Joshi ,  Yue Tan ,  Robert C. Wong

Inventor： Rajiv V. Joshi ,  Yue Tan ,  Robert C. Wong

IPC: G11C7/00

CPC classification number: G11C7/02 ,  G11C11/412 ,  H01L27/11 ,  H01L27/1104

Abstract: A novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment, an 8T SRAM cell structure implements a series gating feature for implementing Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. Particularly, the 8-T approach adds two pass-gates, two series connected transistor devices connected at complementary nodes of two cross-coupled inverters, to control column select and row (word) select. In the other embodiment, a 9T SRAM cell structure includes a transmission gate to implement Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. The 9-T approach adds three transistors to perform ANDING function to separate the row select and column select signal functions. Both methods improve stability by eliminating half-select mode and facilitate rail to rail data transfer in and out of the SRAM cell without disturbing the other cells.

Abstract translation: 一种新颖的半导体SRAM单元结构，其包括至少两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。 在一个实施例中，8T SRAM单元结构实现了用于实现具有增强的稳定性的列选择（CS）和行选择（WL）单元存储访问的串行门控特征。 特别地，8-T方法增加了两个传递门，两个串联的晶体管器件连接在两个交叉耦合的反相器的互补节点处，以控制列选择和行（字）选择。 在另一实施例中，9T SRAM单元结构包括具有增强的稳定性的实现列选择（CS）和行选择（WL）单元存储访问的传输门。 9-T方法增加了三个晶体管来执行ANDING功能，以分离行选择和列选择信号功能。 这两种方法通过消除半选择模式提高稳定性，并有助于轨至轨数据传输进出SRAM单元，而不会干扰其他单元。