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US5780341A Low voltage EEPROM/NVRAM transistors and making method 失效
低电压EEPROM / NVRAM晶体管及制作方法

Low voltage EEPROM/NVRAM transistors and making method
Abstract:
A method for fabricating an electrically programmable memory device which has efficiency of electron injection from the channel to floating gate is provided. A substrate is provided having source and drain region with a channel therebetween. A floating gate structure is formed over portions of the source and drain regions and the channel. The structure includes a dielectric layer and a conductor layer thereover. The channel under the floating gate has both horizontal and vertical components. After forming the vertical and horizontal components, an N- drain region is formed in self-alignment with the vertical channel step region's edge. The depth of the N- drain is greater than the source region.
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