Invention Grant
- Patent Title: Low voltage EEPROM/NVRAM transistors and making method
- Patent Title (中): 低电压EEPROM / NVRAM晶体管及制作方法
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Application No.: US762212Application Date: 1996-12-06
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Publication No.: US5780341APublication Date: 1998-07-14
- Inventor: Seiki Ogura
- Applicant: Seiki Ogura
- Applicant Address: NY Wappingers Falls
- Assignee: Halo LSI Design & Device Technology, Inc.
- Current Assignee: Halo LSI Design & Device Technology, Inc.
- Current Assignee Address: NY Wappingers Falls
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/336 ; H01L21/8247 ; H01L27/115 ; H01L29/423 ; H01L29/788
Abstract:
A method for fabricating an electrically programmable memory device which has efficiency of electron injection from the channel to floating gate is provided. A substrate is provided having source and drain region with a channel therebetween. A floating gate structure is formed over portions of the source and drain regions and the channel. The structure includes a dielectric layer and a conductor layer thereover. The channel under the floating gate has both horizontal and vertical components. After forming the vertical and horizontal components, an N- drain region is formed in self-alignment with the vertical channel step region's edge. The depth of the N- drain is greater than the source region.
Public/Granted literature
- USD334367S Tire Public/Granted day:1993-03-30
Information query
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