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    Deposition methods with time spaced and time abutting precursor pulses
    91.
    发明授权
    Deposition methods with time spaced and time abutting precursor pulses 有权
    具有时间间隔和时间邻接前体脉冲的沉积方法

    公开(公告)号：US07271077B2

    公开(公告)日：2007-09-18

    申请号：US10734999

    申请日：2003-12-12

    Applicant: Eugene Marsh ,  Brian Vaartstra ,  Paul J. Castrovillo ,  Cem Basceri ,  Garo J. Derderian ,  Gurtej S. Sandhu

    Inventor： Eugene Marsh ,  Brian Vaartstra ,  Paul J. Castrovillo ,  Cem Basceri ,  Garo J. Derderian ,  Gurtej S. Sandhu

    IPC: H01L21/36 ,  H01L21/20

    CPC classification number: C30B25/14 ,  C23C16/45527 ,  C30B25/02

    Abstract: An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. The first precursor gas flowing comprises a plurality of first precursor gas pulses. The plurality of first precursor gas pulses comprises at least one total period of time between two immediately adjacent first precursor gas pulses when no gas is fed to the chamber. After forming the first monolayer on the substrate, a second precursor gas different in composition from the first is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.

    Abstract translation: 原子层沉积方法包括将半导体衬底定位在原子层沉积室内。 第一前体气体流到原子层沉积室内的衬底，有效地在衬底上形成第一单层。 第一前体气体流动包括多个第一前体气体脉冲。 多个第一前体气体脉冲包括当没有气体被供给到腔室时在两个紧邻的第一前体气体脉冲之间的至少一个总时间段。 在衬底上形成第一单层之后，组成不同于第一衬底的第二前体气体流入沉积室内的衬底，有效地在第一单层上形成第二单层。 考虑了其他方面和实现。

    One-transistor composite-gate memory
    92.
    发明授权
    One-transistor composite-gate memory 有权
    单晶体管复合栅极存储器

    公开(公告)号：US07268388B2

    公开(公告)日：2007-09-11

    申请号：US10926675

    申请日：2004-08-26

    Applicant: Cem Basceri ,  Gurtej S. Sandhu

    Inventor： Cem Basceri ,  Gurtej S. Sandhu

    IPC: H01L29/792

    CPC classification number: G11C11/5671 ,  G11C8/12 ,  G11C16/0416 ,  G11C16/0466 ,  H01L29/513 ,  H01L29/792

    Abstract: One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.

    Abstract translation: 单晶体管存储器件通过操纵场效应晶体管（FET）的俘获层内的氧空位来促进非易失性数据存储，从而提供晶体管的阈值电压的控制和变化。 可以为各种阈值电压分配数据值，提供将一个或多个位数据存储在单个存储器单元中的能力。 为了控制阈值电压，可以通过在空位内捕获电子来操纵氧空位，从空位释放被俘获的电子，移动捕获层内的空位并湮灭空位。

    Deposition methods
    93.
    发明授权
    Deposition methods 有权
    沉积方法

    公开(公告)号：US07253085B2

    公开(公告)日：2007-08-07

    申请号：US11326739

    申请日：2006-01-05

    Applicant: Eric R. Blomiley ,  Gurtej S. Sandhu ,  Cem Basceri ,  Nirmal Ramaswamy

    Inventor： Eric R. Blomiley ,  Gurtej S. Sandhu ,  Cem Basceri ,  Nirmal Ramaswamy

    IPC: H01L21/36 ,  C30B21/20

    CPC classification number: H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639

    Abstract: The invention includes a method for selective deposition of semiconductor material. A substrate is placed within a reaction chamber. The substrate comprises a first surface and a second surface. The first and second surfaces are exposed to a semiconductor material precursor under conditions in which growth of semiconductor material from the precursor comprises a lag phase prior to a growth phase, and under which it takes longer for the growth phase to initiate on the second surface than on the first surface. The exposure of the first and second surfaces is conducted for a time sufficient for the growth phase to occur on the first surface, but not long enough for the growth phase to occur on the second surface.

    Abstract translation: 本发明包括半导体材料的选择性沉积方法。 将基板放置在反应室内。 基板包括第一表面和第二表面。 第一表面和第二表面在半导体材料前体暴露于其中来自前体的半导体材料的生长在生长阶段之前包含滞后期的条件下，并且在该阶段生长阶段在第二表面上开始需要更长时间比 在第一个表面。 进行第一表面和第二表面的曝光足够长的时间，以使生长阶段在第一表面上发生，但是不足以使生长相发生在第二表面上。

    Capacitor fabrication methods including forming a conductive layer
    95.
    发明授权
    Capacitor fabrication methods including forming a conductive layer 有权
    电容器制造方法包括形成导电层

    公开(公告)号：US07217615B1

    公开(公告)日：2007-05-15

    申请号：US09653149

    申请日：2000-08-31

    Applicant: Garo J. Derderian ,  Gurtej S. Sandhu

    Inventor： Garo J. Derderian ,  Gurtej S. Sandhu

    IPC: H01L21/8242

    CPC classification number: H01L28/56 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02189 ,  H01L21/02197 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/28568 ,  H01L21/31604 ,  H01L28/75 ,  H01L28/84

    Abstract: A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead include chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode and chemisorbing a layer of a second precursor at least one monolayer thick on the first precursor layer, a chemisorption product of the first and second precursor layers being comprised by a layer of a conductive barrier material. The barrier layer may be sufficiently thick and dense to reduce oxidation of the first electrode by oxygen diffusion from over the barrier layer. An alternative method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer. The method may further include forming rugged polysilicon over the substrate, the first electrode being over the rugged polysilicon. Accordingly, the outer surface area of the first electrode can be at least 30% greater than the outer surface area of the substrate without the first electrode including polysilicon.

    Abstract translation: 电容器制造方法可以包括在第一电极上的氧扩散的原子层沉积导电阻挡层。 一种方法可以包括在第一电极上化学吸附至少一层单层的第一前体层，并化学吸附第一前体层上至少一层单层的第二前体层，第一和第二前体层的化学吸附产物 由导电阻挡材料层组成。 阻挡层可以是足够厚且致密的，以通过从阻挡层上方的氧扩散来减少第一电极的氧化。 替代方法可以包括在衬底上形成第一电容器电极，第一电极具有每单位面积的内表面积和每单位面积的外表面积，其大于衬底每单位面积的外表面积。 可以在电介质层上形成电容器电介质层和第二电容器电极。 该方法还可以包括在衬底上形成坚固的多晶硅，第一电极在坚固的多晶硅之上。 因此，第一电极的外表面积可以比不含第一电极包括多晶硅的衬底的外表面积大至少30％。

    Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks
    96.
    发明授权
    Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks 有权
    形成和利用抗反射材料层的半导体加工方法，以及形成晶体管栅叠层的方法

    公开(公告)号：US07151054B2

    公开(公告)日：2006-12-19

    申请号：US10805557

    申请日：2004-03-19

    Applicant: Gurtej S. Sandhu ,  Sujit Sharan

    Inventor： Gurtej S. Sandhu ,  Sujit Sharan

    IPC: H01L21/4763

    CPC classification number: G03F7/091 ,  H01L21/0214 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/28123 ,  H01L21/3145

    Abstract: In one aspect, the invention includes a semiconductor processing method comprising exposing silicon, nitrogen and oxygen in gaseous form to a high density plasma during deposition of a silicon, nitrogen and oxygen containing solid layer over a substrate.In another aspect, the invention includes a gate stack forming method, comprising: a) forming a polysilicon layer over a substrate; b) forming a metal silicide layer over the polysilicon layer; c) depositing an antireflective material layer over the metal silicide utilizing a high density plasma; d) forming a layer of photoresist over the antireflective material layer; e) photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist; and f) transferring a pattern from the patterned masking layer to the antireflective material layer, metal silicide layer and is polysilicon layer to pattern the antireflective material layer, metal silicide layer and polysilicon layer into a gate stack.

    Abstract translation: 在一个方面，本发明包括一种半导体处理方法，包括在衬底上沉积含硅，含氮和氧的固体层时，将硅，氮和氧气体暴露于高密度等离子体。 在另一方面，本发明包括一种栅堆叠形成方法，包括：a）在衬底上形成多晶硅层; b）在所述多晶硅层上形成金属硅化物层; c）利用高密度等离子体在金属硅化物上沉积防反射材料层; d）在抗反射材料层上形成一层光致抗蚀剂; e）光刻地图案化所述光致抗蚀剂层以从所述光致抗蚀剂层形成图案化掩模层; 以及f）将图案从图案化掩模层转移到抗反射材料层，金属硅化物层，并且是将抗反射材料层，金属硅化物层和多晶硅层图案化成栅叠层的多晶硅层。

    Methods of forming intermediate semiconductor device structures using spin-on, photopatternable, interlayer dielectric materials
    99.
    发明授权
    Methods of forming intermediate semiconductor device structures using spin-on, photopatternable, interlayer dielectric materials 有权
    使用旋涂，光图案化，层间介电材料形成中间半导体器件结构的方法

    公开(公告)号：US07060637B2

    公开(公告)日：2006-06-13

    申请号：US10435791

    申请日：2003-05-12

    Applicant: Weimin Li ,  Gurtej S. Sandhu

    Inventor： Weimin Li ,  Gurtej S. Sandhu

    IPC: H01L21/47 ,  C08J7/04

    CPC classification number: G03F7/095 ,  G03F7/0757 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/311 ,  Y10T428/31663

    Abstract: A cap layer that enables a photopatternable, spin-on material to be used in the formation of semiconductor device structures at wavelengths that were previously unusable. The photopatternable, spin-on material is applied as a layer to a semiconductor substrate. The cap layer and a photoresist layer are each formed over the photopatternable layer. The cap layer absorbs or reflects radiation and protects the photopatternable layer from a first wavelength of radiation used in patterning the photoresist layer. The photopatternable, spin-on material is convertible to a silicon dioxide-based material upon exposure to a second wavelength of radiation.

    Abstract translation: 能够使光可图案化的旋涂材料用于以前不可用的波长形成半导体器件结构的盖层。 将可光刻图案的旋涂材料作为层施加到半导体衬底。 覆盖层和光致抗蚀剂层各自形成在光图案化层上。 盖层吸收或反射辐射，并保护光致图案层免受用于图案化光致抗蚀剂层的第一波长的辐射。 照射图案化的旋涂材料在暴露于第二波长辐射时可转换为二氧化硅基材料。

    Enhanced surface area capacitor fabrication methods
    100.
    发明授权
    Enhanced surface area capacitor fabrication methods 失效
    增强表面积电容器制造方法

    公开(公告)号：US07053432B2

    公开(公告)日：2006-05-30

    申请号：US09882534

    申请日：2001-06-14

    Applicant: Garo J. Derderian ,  Gurtej S. Sandhu

    Inventor： Garo J. Derderian ,  Gurtej S. Sandhu

    IPC: H01L27/108

    CPC classification number: H01L21/3162 ,  H01L21/02178 ,  H01L21/0228 ,  H01L28/56 ,  H01L28/84 ,  H01L28/91

    Abstract: A capacitor fabrication method may include forming a first capacitor electrode over a substrate and atomic layer depositing an insulative barrier layer to oxygen diffusion over the first electrode. A capacitor dielectric layer may be formed over the first electrode and a second capacitor electrode may be formed over the dielectric layer. The barrier layer may include Al2O3. A capacitor fabrication method may also include forming a first capacitor electrode over a substrate, chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode, and chemisorbing a layer of a second precursor at least one monolayer thick on the first precursor layer. A chemisorption product of the first and second precursors may be comprised by a layer of an insulative barrier material. The first precursor may include H2O and the second precursor may include trimethyl aluminum.

    Abstract translation: 电容器制造方法可以包括在衬底上形成第一电容器电极，并且将原子层沉积在第一电极上的氧扩散的绝缘阻挡层上。 可以在第一电极上形成电容器电介质层，并且可以在电介质层上形成第二电容器电极。 阻挡层可以包括Al 2 O 3 3。 电容器制造方法还可以包括在衬底上形成第一电容器电极，在第一电极上化学吸附至少一层单层厚度的第一前体层，以及化学吸附第一前体上的至少一层单层的第二前体层 层。 第一和第二前体的化学吸附产物可以由绝缘屏障材料层构成。 第一前体可以包括H 2 O，第二前体可以包括三甲基铝。

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