公开(公告)号：US20160109813A1

公开(公告)日：2016-04-21

申请号：US14581632

申请日：2014-12-23

Applicant: APPLIED MATERIALS, INC.

Inventor： Sang Ki NAM ,  Peng XIE ,  Qiwei LIANG ,  Ludovic GODET

IPC: G03F7/20 ,  G03F7/40

CPC classification number: G03F7/70733 ,  G03F7/38 ,  G03F7/40 ,  G03F7/70325

Abstract: A method of processing a substrate is disclosed herein. The method includes applying a photoresist layer comprising a photoacid generator to a substrate, wherein a first portion of the photoresist layer has been exposed unprotected by a photomask to a radiation light in a lithographic exposure process. The method also includes applying an electric field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction, wherein the electric field is applied by a first alternating pair of a positive voltage electrode and a negative voltage electrode and a second alternating pair of a positive voltage electrode and a negative voltage electrode.

Abstract translation: 本文公开了一种处理衬底的方法。 该方法包括将包含光致酸产生剂的光致抗蚀剂层施加到基底上，其中光致抗蚀剂层的第一部分已经在光刻曝光工艺中被光掩模曝光而不被辐射光照射。 该方法还包括施加电场以改变基本上沿垂直方向从光致酸产生器产生的光酸的移动，其中电场由正电压电极和负电压电极的第一交替对和第二交替对施加 的正电压电极和负电压电极。

公开(公告)号：US20160011515A1

公开(公告)日：2016-01-14

申请号：US14478403

申请日：2014-09-05

Applicant: Applied Materials, Inc.

Inventor： Peng XIE ,  Ludovic GODET

IPC: G03F7/26 ,  G03F7/20

CPC classification number: G03F7/26 ,  G03F7/0045 ,  G03F7/091 ,  G03F7/094 ,  G03F7/168 ,  G03F7/2051 ,  G03F7/38

Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate, the method includes applying a photoresist layer comprising a photoacid generator to a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.

Abstract translation: 提供了通过光刻形成的线中的线边缘/宽度粗糙度最小化的方法和装置。 在一个实例中，一种处理衬底的方法，所述方法包括将包含光致酸产生剂的光致抗蚀剂层施加到衬底上，将未被光掩模保护的光致抗蚀剂层的第一部分暴露于光刻曝光工艺中的辐射光，并施加 电场或磁场，以改变基本上沿垂直方向从光致酸发生器产生的光酸的运动。

公开(公告)号：US20150315707A1

公开(公告)日：2015-11-05

申请号：US14267865

申请日：2014-05-01

Applicant: Applied Materials, Inc.

Inventor： Jun XUE ,  Jingjing LIU ,  Yongmei CHEN ,  Ludovic GODET ,  Chentsau YING ,  Shambhu N. ROY

IPC: C23C16/56 ,  C23C16/505 ,  C23C16/455 ,  C23C16/27 ,  C23C16/46

CPC classification number: C23C16/56 ,  C23C16/27 ,  C23C16/272 ,  C23C16/452 ,  C23C16/45523 ,  C23C16/45557 ,  C23C16/46 ,  C23C16/505

Abstract: Methods for making a nanocrystalline diamond layer are disclosed herein. A method of forming a layer can include activating a deposition gas comprising an alkane and a hydrogen containing gas at a first pressure, delivering the activated deposition gas to the substrate at a second pressure which is less than the first pressure, forming a nanocrystalline diamond layer, treating the layer with an activated hydrogen containing gas to remove one or more polymers from the surface and repeating the cycle to achieve a desired thickness.

Abstract translation: 本文公开了制备纳米晶体金刚石层的方法。 形成层的方法可以包括在第一压力下激活包括烷烃和含氢气体的沉积气体，在小于第一压力的第二压力下将活化的沉积气体输送到衬底，形成纳米晶体金刚石层 用活化的含氢气体处理层以从表面去除一种或多种聚合物并重复该循环以达到所需的厚度。

公开(公告)号：US20150279974A1

公开(公告)日：2015-10-01

申请号：US14622647

申请日：2015-02-13

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Christopher HATEM ,  Matthew D. SCOTNEY-CASTLE ,  Martin A. HILKENE

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/223

CPC classification number: H01L29/66803 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/30 ,  H01L21/30604 ,  H01L21/3065

Abstract: Embodiments of the present invention provide methods for forming fin structure with desired materials using a conversion process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming a fin structure on a substrate includes performing an directional plasma process on a fin structure formed from a substrate comprising a first type of atoms, the directional plasma process dopes a second type of atoms on sidewalls of the fin structure, performing a surface modification process to form a surface modified layer on the sidewalls of the fin structure reacting with the first type of atoms, replacing the first type of the atoms with the second type of the atoms in the fin structure during the surface modification process, and forming the fin structure including the second type of the atoms on the substrate.

Abstract translation: 本发明的实施例提供了使用用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠的转换工艺来形成具有所需材料的鳍结构的方法。 在一个实施例中，在衬底上形成翅片结构的方法包括对由包括第一类型的原子的衬底形成的鳍结构执行定向等离子体处理，所述定向等离子体工艺在鳍的侧壁上掺杂第二类型的原子 结构，进行表面改性处理以在与第一类型的原子反应的翅片结构的侧壁上形成表面改性层，在表面改性期间用翅片结构中的第二类型的原子代替第一类型的原子 处理，并且形成包括基板上的第二类型的原子的翅片结构。

公开(公告)号：US20150194317A1

公开(公告)日：2015-07-09

申请号：US14574928

申请日：2014-12-18

Applicant: Applied Materials, Inc.

Inventor： PRAMIT MANNA ,  Abhijit Basu MALLICK ,  Ludovic GODET ,  Yongmei CHEN ,  Jun XUE ,  Mukund SRINIVASAN ,  Ellie Y. YIEH ,  Srinivas D. NEMANI

IPC: H01L21/308 ,  H01L27/115 ,  H01L27/108

CPC classification number: H01L21/3086 ,  H01L21/31144 ,  H01L21/31155

Abstract: Embodiments described herein provide for a method of forming an etch selective hardmask. An amorphous carbon hardmask is implanted with various dopants to increase the hardness and density of the hardmask. The ion implantation of the amorphous carbon hardmask also maintains or reduces the internal stress of the hardmask. The etch selective hardmask generally provides for improved patterning in advanced NAND and DRAM devices.

Abstract translation: 本文描述的实施例提供了形成蚀刻选择性硬掩模的方法。 非晶碳硬掩模被植入各种掺杂剂以增加硬掩模的硬度和密度。 无定形碳硬掩模的离子注入还保持或减少硬掩模的内部应力。 蚀刻选择性硬掩模通常提供高级NAND和DRAM器件中的改进的图案化。

公开(公告)号：US20150118822A1

公开(公告)日：2015-04-30

申请号：US14068312

申请日：2013-10-31

Applicant: APPLIED MATERIALS, INC.

Inventor： Ying ZHANG ,  Hua CHUNG ,  Srinivas D. NEMANI ,  Ludovic GODET

IPC: H01L21/762 ,  H01L21/265

CPC classification number: H01L21/76224 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/6831 ,  H01L29/66795

Abstract: Embodiments of the present invention provide a methods for forming silicon recess structures in a substrate with good process control, particularly suitable for manufacturing three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming recess structures in a substrate includes etching a first portion of a substrate defined by a second portion formed in the substrate until a doping layer formed in the substrate is exposed.

Abstract translation: 本发明的实施例提供了一种用于在具有良好的工艺控制的衬底中形成硅凹陷结构的方法，特别适用于制造用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠。 在一个实施例中，在衬底中形成凹陷结构的方法包括蚀刻由形成在衬底中的第二部分限定的衬底的第一部分，直到形成在衬底中的掺杂层露出。

公开(公告)号：US20240409449A1

公开(公告)日：2024-12-12

申请号：US18804592

申请日：2024-08-14

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng LEI ,  Mahendran CHIDAMBARAM ,  Kangkang WANG ,  Ludovic GODET ,  Visweswaren SIVARAMAKRISHNAN

IPC: C03B33/02 ,  B23K26/00 ,  B23K26/0622 ,  B23K26/08 ,  B23K26/55 ,  B23K101/40 ,  B23K103/00 ,  C03B33/10 ,  C03C23/00

Abstract: A method includes forming a plurality of voids within a substrate along a dicing path by exposing the substrate to a first burst of laser pulses at a first location along the dicing path of a respective waveguide combiner. The substrate has a plurality of waveguides. Each laser pulse within the first burst forms a respective void within a first column at the first location to form the plurality of voids. The method further includes exposing the substrate to a second burst of laser pulses at a second location along the dicing path of the respective waveguide combiner. Each laser pulse within the second burst forms the respective void within a second column at the second location to form the plurality of voids. The first column and the second column are spaced by a pitch between a center of the first column and the second column along the dicing path.

公开(公告)号：US20240270007A1

公开(公告)日：2024-08-15

申请号：US18167682

申请日：2023-02-10

Applicant: Applied Materials, Inc.

Inventor： Yingdong LUO ,  Jinyu LU ,  Takashi KURATOMI ,  Alexia Adilene PORTILLO RIVERA ,  Xiaopei DENG ,  Zhengping YAO ,  Daihua ZHANG ,  Rami HOURANI ,  Ludovic GODET

IPC: B41M3/00 ,  B41J11/00 ,  G02B27/01

CPC classification number: B41M3/003 ,  B41J11/00212 ,  G02B27/0172

Abstract: Embodiments of the present disclosure generally relate to optical devices. More specifically, embodiments described herein relate to optical devices and methods of manufacturing a patterned optical device film on an optical device substrate. According to certain embodiments, an inkjet deposition process is used to deposit a patterned inkjet coating layer on the optical device substrate. A deposition process may then be used to deposit an optical device material on the patterned inkjet coating and the optical device substrate. The patterned inkjet coating on the optical device substrate may then be washed with an appropriate detergent to lift-off the patterned inkjet coating layer from the optical device substrate to form the patterned optical device film.

公开(公告)号：US20240184024A1

公开(公告)日：2024-06-06

申请号：US18439434

申请日：2024-02-12

Applicant: Applied Materials, Inc.

Inventor： Michael Yu-tak YOUNG ,  Ludovic GODET ,  Robert Jan VISSER ,  Naamah ARGAMAN ,  Christopher Dennis BENCHER ,  Wayne MCMILLAN

IPC: G02B5/18 ,  G02B26/08 ,  G02B30/26 ,  G03F7/00

CPC classification number: G02B5/1842 ,  G02B5/1857 ,  G02B26/0808 ,  G02B30/26 ,  G02B5/1876 ,  G03F7/0037

Abstract: Embodiments herein describe a sub-micron 3D diffractive optics element and a method for forming the sub-micron 3D diffractive optics element. In a first embodiment, a method is provided for forming a sub-micron 3D diffractive optics element on a film stack disposed on a substrate without planarization. The method includes forming a hardmask on a top surface of a film stack. Forming a mask material on a portion of the top surface and a portion of the hardmask. Etching the top surface. Trimming the mask. Etching the top surface again. Trimming the mask a second time. Etching the top surface yet again and then stripping the mask material.

公开(公告)号：US20240126012A1

公开(公告)日：2024-04-18

申请号：US18381604

申请日：2023-10-18

Applicant: Applied Materials, Inc.

Inventor： Yingdong LUO ,  Zhengping YAO ,  Daihua ZHANG ,  David Alexander SELL ,  Jingyi YANG ,  Xiaopei DENG ,  Kevin MESSER ,  Samarth BHARGAVA ,  Rami HOURANI ,  Ludovic GODET

IPC: G02B6/122 ,  G02B6/12 ,  G02B6/124 ,  G02B6/13 ,  G02B27/00

CPC classification number: G02B6/1228 ,  G02B6/12004 ,  G02B6/124 ,  G02B6/13 ,  G02B27/0081

Abstract: Embodiments of the present disclosure generally relate to methods for forming a waveguide. Methods may include measuring a waveguide substrate, the waveguide having a substrate thickness distribution; and depositing an index-matched layer onto a surface of the waveguide, the index-matched layer having a first surface disposed on the waveguide substrate and a second surface opposing the first surface, wherein the index-matched layer is disposed only over a portion of the waveguide substrate, and a device slope of a second surface of the index-matched layer is substantially the same as the waveguide slope of the first surface of the waveguide.