公开(公告)号：US20130168841A1

公开(公告)日：2013-07-04

申请号：US13340430

申请日：2011-12-29

Applicant: Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K.V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

Inventor： Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K.V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

IPC: H01L23/495 ,  H01L21/326 ,  H05K1/11 ,  B82Y99/00

CPC classification number: H01L23/49827 ,  B82Y10/00 ,  H01L21/485 ,  H01L21/486 ,  H01L23/49822 ,  H01L2224/16225 ,  H05K1/029 ,  H05K3/4038 ,  H05K2201/0248 ,  H05K2201/026 ,  H05K2201/0323 ,  H05K2201/10378 ,  H05K2203/104 ,  H05K2203/105

Abstract: An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable interposer. The conductive particles are capable of forming an aligned configuration between the top and bottom interface electrodes in response to application of an energy field to the programmable interposer so as to electrically connect the top and bottom interface electrodes. The conductive particles can have a conductive outer surface. Also, the conductive particles can be spherical. The conductive particles can be within a bulk material in an interface layer in the programmable interposer, and the bulk material can be cured to secure programmed paths between the top and bottom interface electrodes.

Abstract translation: 本公开的示例性实现包括具有顶部和底部接口电极和散布在可编程插值器内的导电粒子的可编程插值器。 响应于将能量场施加到可编程内插器，导电颗粒能够在顶部和底部界面电极之间形成对准的构造，以便电连接顶部和底部界面电极。 导电颗粒可具有导电外表面。 此外，导电粒子可以是球形的。 导电颗粒可以在可编程插入器中的界面层中的体积材料内，并且可以固化块状材料以确保顶部和底部界面电极之间的编程路径。

公开(公告)号：US20130082330A1

公开(公告)日：2013-04-04

申请号：US13250563

申请日：2011-09-30

Applicant: Wei Xia ,  Xiangdong Chen

Inventor： Wei Xia ,  Xiangdong Chen

IPC: H01L27/092 ,  H01L21/60 ,  H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L24/13 ,  H01L24/14 ,  H01L27/0629 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2924/12035 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.

Abstract translation: 垂直堆叠的平面结齐纳二极管与外延生长的FET升高的S / D端子同时形成。 齐纳二极管的结构和工艺与Gate-Last高k FET结构和工艺兼容。 二极管和晶体管结构的横向分离由改进的STI屏蔽提供。 不需要额外的光刻步骤。 在一些实施例中，最上面的二极管端子的非结面用镍硅化，以另外作为铜扩散阻挡层。

公开(公告)号：US08363445B2

公开(公告)日：2013-01-29

申请号：US13283267

申请日：2011-10-27

Applicant: Frank Hui ,  Xiangdong Chen ,  Wei Xia

Inventor： Frank Hui ,  Xiangdong Chen ,  Wei Xia

IPC: G11C17/00

CPC classification number: G11C17/16 ,  G11C17/18 ,  H01L27/115

Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

Abstract translation: 根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的可移位阈值电压晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。 可移位阈值电压晶体管具有漏极和栅极短路在一起。 编程操作导致响应于位线和字线上的编程电压而发生可移位阈值电压晶体管的阈值电压的永久偏移。 在一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管是PFET。 在另一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管也是NFET。 编程电压可导致阈值电压的绝对值永久增加至少50.0毫伏。

公开(公告)号：US20120273894A1

公开(公告)日：2012-11-01

申请号：US13094873

申请日：2011-04-27

Applicant: Xiangdong Chen ,  Laegu Kang ,  Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony

Inventor： Xiangdong Chen ,  Laegu Kang ,  Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/8258 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/7843

Abstract: An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.

Abstract translation: 集成电路结构在衬底上包括至少一对互补晶体管。 一对互补晶体管包括第一晶体管和第二晶体管。 此外，在第一晶体管和第二晶体管上只有一个应力产生层，并且在第一晶体管和第二晶体管上施加拉伸应变力。 第一晶体管具有第一沟道区，第一沟道区上的栅极绝缘体，以及第一沟道区和栅绝缘体之间的氘区。 第二晶体管具有锗掺杂沟道区以及锗掺杂沟道区上的相同栅极绝缘体以及锗掺杂沟道区和栅绝缘体之间的相同氘区。

公开(公告)号：US20120217613A1

公开(公告)日：2012-08-30

申请号：US13466986

申请日：2012-05-08

Applicant: Wei Xia ,  Xiangdong Chen ,  Akira Ito

Inventor： Wei Xia ,  Xiangdong Chen ,  Akira Ito

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure.

Abstract translation: 根据一个示例性实施例，一种用于形成一次性可编程金属熔丝结构的方法包括在衬底上形成金属熔丝结构，所述金属熔丝结构包括位于介电段和多晶硅段之间的栅极金属段，栅极金属 熔丝形成在栅极金属段的一部分中。 该方法还包括掺杂多晶硅段以便形成由未掺杂多晶硅部分分开的第一和第二掺杂多晶硅部分，其中在一个实施例中，栅极金属熔丝与未掺杂的多晶硅部分基本上共同延伸。 该方法还可以包括在第一掺杂多晶硅部分上形成第一硅化物部分和在第二掺杂多晶硅部分上形成第二硅化物部分，其中第一和第二硅化物部分形成一次性可编程金属熔丝结构的相应端子。

公开(公告)号：US08062951B2

公开(公告)日：2011-11-22

申请号：US11953445

申请日：2007-12-10

Applicant: Xiangdong Chen ,  Kenneth J. Stein ,  Thomas A. Wallner

Inventor： Xiangdong Chen ,  Kenneth J. Stein ,  Thomas A. Wallner

IPC: H01L29/76

CPC classification number: H01L21/76232 ,  H01L29/66651

Abstract: An epitaxial layer of silicon (Si) or silicon-germanium (SiGe) extends over the edge of silicon trench isolation (STI), thereby increasing the effective width of an active silicon region (RX) bordered by the STI. The RX region may have a crystal orientation. An effective width of an FET device formed in the RX region may be increased, therefore performance may be improved with same density. Isolation may not be degraded since RX-to-RX distance is same at bottom. Junction capacitance may be reduced since part of the RX is on STI.

Abstract translation: 硅（Si）或硅锗（SiGe）的外延层在硅沟槽隔离（STI）的边缘上延伸，从而增加由STI界定的有源硅区域（RX）的有效宽度。 RX区域可以具有<100>晶体取向。 可以增加在RX区域中形成的FET器件的有效宽度，因此可以以相同的密度提高性能。 隔离可能不会降低，因为RX至RX距离在底部相同。 由于RX的一部分在STI上，结电容可能会降低。

公开(公告)号：US08003454B2

公开(公告)日：2011-08-23

申请号：US12125855

申请日：2008-05-22

Applicant: Da Zhang ,  Srikanth B. Samavedam ,  Voon-Yew Thean ,  Xiangdong Chen

Inventor： Da Zhang ,  Srikanth B. Samavedam ,  Voon-Yew Thean ,  Xiangdong Chen

IPC: H01L21/336 ,  H01L21/337

CPC classification number: H01L21/823807 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.

Abstract translation: 半导体工艺和装置包括通过选择性地缓解PMOS器件区域（97）中的双轴拉伸应变半导体层（90）的一部分，在晶体管的沟道区域中形成具有增强的空穴迁移率的NMOS和PMOS晶体管（24,34） 以形成松弛半导体层（91），然后在形成覆盖沟道区域的NMOS和PMOS栅极结构（26,36）之前外延生长双轴向应力硅锗沟道区域层（22），然后沉积 接触蚀刻停止层（53-56）在NMOS和PMOS栅极结构之上。 也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。

公开(公告)号：US07968910B2

公开(公告)日：2011-06-28

申请号：US12103301

申请日：2008-04-15

Applicant: Xiangdong Chen ,  Thomas W. Dyer ,  Haining S. Yang

Inventor： Xiangdong Chen ,  Thomas W. Dyer ,  Haining S. Yang

IPC: H01L21/02 ,  H01L27/12

CPC classification number: H01L21/823807 ,  H01L21/8258 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of a substrate. The first semiconductor region can be grown laterally adjacent to a second semiconductor region which has a lattice constant smaller than that of silicon. Layers consisting essentially of silicon can be grown epitaxially onto exposed major surfaces of the first and second semiconductor regions after which gates can be formed which overlie the epitaxially grown silicon layers. Portions of the first and second semiconductor regions adjacent to the gates can be removed to form recesses. Regions consisting essentially of silicon can be grown within the recesses to form embedded silicon regions. Source and drain regions then can be formed in the embedded silicon regions. The difference between the lattice constant of silicon and that of the underlying first and second regions results in tensile stressed silicon over the first semiconductor region and compressive stressed silicon over the second semiconductor region.

Abstract translation: 提供了制造互补应力半导体器件的方法，例如具有拉伸应力通道的NFET和具有压应力通道的PFET。 在这种方法中，可以在衬底的下面的半导体区域外延生长具有大于硅的晶格常数的第一半导体区域。 第一半导体区域可以与具有比硅的晶格常数小的晶格常数的第二半导体区域横向生长。 基本上由硅组成的层可以外延生长到第一和第二半导体区域的暴露的主表面上，之后可以形成覆盖外延生长的硅层的栅极。 可以去除与栅极相邻的第一和第二半导体区域的部分以形成凹部。 基本上由硅组成的区域可以在凹槽内生长以形成嵌入的硅区域。 然后可以在嵌入的硅区域中形成源区和漏区。 硅的晶格常数和下面的第一和第二区域的晶格常数之间的差异导致第一半导体区域上的拉伸应力硅和第二半导体区域上的压应力硅。

公开(公告)号：US20110108903A1

公开(公告)日：2011-05-12

申请号：US12590370

申请日：2009-11-06

Applicant: Wei Xia ,  Xiangdong Chen ,  Frank Hui

Inventor： Wei Xia ,  Xiangdong Chen ,  Frank Hui

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L21/28273 ,  H01L27/11526 ,  H01L27/11546

Abstract: According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.

Abstract translation: 根据一个示例性实施例，一种用于在半导体管芯中制造快闪存储器单元的方法包括：在衬底的存储器区域中形成覆盖浮置栅极堆叠的控制栅极堆叠，其中浮置栅极堆叠包括覆盖一部分 电介质层。 浮栅包括金属一层的一部分，电介质一层包括第一高k电介质材料。 控制栅极堆叠可以包括包括金属两层的一部分的控制栅极，其中金属一层可以包括与金属两层不同的金属。

公开(公告)号：US20110107192A1

公开(公告)日：2011-05-05

申请号：US11908251

申请日：2006-01-03

Applicant: Shuzhi Ge ,  Xiangdong Chen ,  Xiaoyan Han

Inventor： Shuzhi Ge ,  Xiangdong Chen ,  Xiaoyan Han

IPC: G06F17/00

CPC classification number: A61K31/12

Abstract: An authoring tool for creating an electronic document, a method for creating the electronic document, a data storage medium for instructing a computer to execute the method for creating the electronic document and a data storage medium for instructing a computer to display the electronic document. The authoring tool comprises; a template module for selecting a template for the electronic document, the template comprising one or more display pages; a content management module for arranging one or more media files on each display page with selected interrelationships between the media files; a generating module for creating an electronic page file for each display page, wherein the media files are embedded in the respective electronic page files based on the selected interrelationships and in a manner such that each electronic page file includes interrelationship data defining the interrelationships of the embedded media files in said each electronic page file with other media files in said each electronic page file and with other media files in other electronic page files of the electronic document; and a binding module for electronically binding the respective electronic page files so as to create the electronic document.

Abstract translation: 用于创建电子文档的创作工具，用于创建电子文档的方法，用于指示计算机执行创建电子文档的方法的数据存储介质和用于指示计算机显示电子文档的数据存储介质。 创作工具包括 用于选择所述电子文档的模板的模板模块，所述模板包括一个或多个显示页面; 内容管理模块，用于在每个显示页面上布置一个或多个媒体文件，其中媒体文件之间具有选定的相互关系; 用于为每个显示页面创建电子页面文件的生成模块，其中基于所选择的相互关系将媒体文件嵌入在相应的电子页面文件中，并且以这样的方式使得每个电子页面文件包括定义嵌入的相互关系的相互关系数据 所述每个电子页面文件中的媒体文件与所述每个电子页面文件中的其他媒体文件以及电子文档的其他电子页面文件中的其他媒体文件; 以及用于电子地绑定各个电子页面文件以便创建电子文档的装订模块。