公开(公告)号：US20060206770A1

公开(公告)日：2006-09-14

申请号：US11419696

申请日：2006-05-22

Applicant: Jian Chen ,  Tomoharu Tanaka

Inventor： Jian Chen ,  Tomoharu Tanaka

IPC: G11C29/00

CPC classification number: G11C11/5635 ,  G06F11/1068 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/3427 ,  G11C16/3459 ,  G11C16/349 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each block has endured is stored in one location within the block, such as in spare cells of only one page or distributed among header regions of multiple pages. The page or pages containing the block cycle count are initially read from each block that is being erased, the cycle count temporarily stored, the block erased and an updated cycle count is then written back into the block location. User data is then programmed into individual pages of the block as necessary. The user data is preferably stored in more than two states per memory cell storage element, in which case the cycle count can be stored in binary in a manner to speed up the erase process and reduce disturbing effects on the erased state that writing the updated cycle count can cause. An error correction code calculated from the cycle count may be stored with it, thereby allowing validation of the stored cycle count.

Abstract translation: 在被分成具有存储在每个块中的多页用户数据的存储单元的单独可擦除块的快闪EEPROM系统中，每个块已经承受的擦除周期数的计数被存储在块内的一个位置中， 如在仅一页的备用单元中或分布在多页的标题区之间。 最初从被擦除的每个块读取包含块循环计数的页面，临时存储循环计数，擦除块，然后将更新的循环计数写回到块位置。 然后根据需要将用户数据编程到块的各个页面中。 用户数据优选地存储在每个存储器单元存储元件的多于两个状态中，在这种情况下，周期计数可以以加速擦除处理的方式以二进制存储，并且减少写入更新周期的擦除状态的干扰效应 计数可以造成。 可以与循环计数一起存储从周期计数中计算的纠错码，从而允许验证存储的循环计数。

公开(公告)号：US20060203558A1

公开(公告)日：2006-09-14

申请号：US11417185

申请日：2006-05-04

Applicant: Tomoharu Tanaka ,  Jian Chen

Inventor： Tomoharu Tanaka ,  Jian Chen

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  G11C16/3481 ,  G11C2211/5621 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

Abstract translation: 非易失性半导体存储器件包括电数据可重写非易失性半导体存储单元和用于在存储单元中写入数据的写入电路，写入电路通过提供写入电压Vpgm和写入控制将数据写入存储单元 电压VBL到存储器单元，响应于存储单元的第一写入状态的到来改变写入控制电压VBL的值，继续写入存储单元中的数据，并且禁止写入数据的任何操作 该存储单元响应于存储单元的第二写入状态的进入而进一步将写入控制电压VBL的值改变为Vdd。

公开(公告)号：US20060176088A1

公开(公告)日：2006-08-10

申请号：US11389048

申请日：2006-03-27

Applicant: Masaki Fujiu ,  Tomoharu Tanaka

Inventor： Masaki Fujiu ,  Tomoharu Tanaka

IPC: H03L7/00

CPC classification number: H03K17/22 ,  H03K17/223

Abstract: A semiconductor integrated circuit device with a power-on detecting circuit, wherein the power-on detecting circuit includes: first and second power supply terminals between which an external power supply voltage is to be supplied; a first diode circuit having a first resistor and a first diode connected in series between the first and second power supply terminals, an interconnect node between the first resistor and first diode serving as a first voltage detecting node; a second diode circuit having second and third resistors and a second diode connected in series between the first and second power supply terminals, the second diode having a current drivability larger than the first diode, an interconnect node between the second and third resistors serving as a second voltage detecting node; and a first comparator for detecting a voltage of the second voltage detecting node becoming higher than that of the first voltage detecting node to output a power-on signal.

公开(公告)号：US07085161B2

公开(公告)日：2006-08-01

申请号：US11003046

申请日：2004-12-02

Applicant: Jian Chen ,  Tomoharu Tanaka

Inventor： Jian Chen ,  Tomoharu Tanaka

IPC: G11C16/04 ,  G11C16/06 ,  G11C8/00 ,  G11C7/10

CPC classification number: G11C11/5635 ,  G06F11/1068 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/3427 ,  G11C16/3459 ,  G11C16/349 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each block has endured is stored in one location within the block, such as in spare cells of only one page or distributed among header regions of multiple pages. The page or pages containing the block cycle count are initially read from each block that is being erased, the cycle count temporarily stored, the block erased and an updated cycle count is then written back into the block location. User data is then programmed into individual pages of the block as necessary. The user data is preferably stored in more than two states per memory cell storage element, in which case the cycle count can be stored in binary in a manner to speed up the erase process and reduce disturbing effects on the erased state that writing the updated cycle count can cause. An error correction code calculated from the cycle count may be stored with it, thereby allowing validation of the stored cycle count.

Abstract translation: 在被分成具有存储在每个块中的多页用户数据的存储单元的单独可擦除块的快闪EEPROM系统中，每个块已经承受的擦除周期数的计数被存储在块内的一个位置中， 如在仅一页的备用单元中或分布在多页的标题区之间。 最初从被擦除的每个块读取包含块循环计数的页面，临时存储循环计数，擦除块，然后将更新的循环计数写回到块位置。 然后根据需要将用户数据编程到块的各个页面中。 用户数据优选地存储在每个存储器单元存储元件的多于两个状态中，在这种情况下，周期计数可以以加速擦除处理的方式以二进制存储，并且减少写入更新周期的擦除状态的干扰效应 计数可以造成。 可以与循环计数一起存储从周期计数中计算的纠错码，从而允许验证存储的循环计数。

公开(公告)号：US20060146610A1

公开(公告)日：2006-07-06

申请号：US11336944

申请日：2006-01-23

Applicant: Ken Takeuchi ,  Tomoharu Tanaka ,  Noboru Shibata

Inventor： Ken Takeuchi ,  Tomoharu Tanaka ,  Noboru Shibata

IPC: G11C16/04

CPC classification number: G11C16/3418 ,  G11C7/1051 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3431 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5649 ,  G11C2211/565 ,  G11C2216/14

Abstract: Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.

公开(公告)号：US07042787B2

公开(公告)日：2006-05-09

申请号：US10935581

申请日：2004-09-08

Applicant: Masaki Fujiu ,  Tomoharu Tanaka

Inventor： Masaki Fujiu ,  Tomoharu Tanaka

IPC: G11C7/00

CPC classification number: H03K17/22 ,  H03K17/223

Abstract: A semiconductor integrated circuit device with a power-on detecting circuit, wherein the power-on detecting circuit includes: first and second power supply terminals between which an external power supply voltage is to be supplied; a first diode circuit having a first resistor and a first diode connected in series between the first and second power supply terminals, an interconnect node between the first resistor and first diode serving as a first voltage detecting node; a second diode circuit having second and third resistors and a second diode connected in series between the first and second power supply terminals, the second diode having a current drivability larger than the first diode, an interconnect node between the second and third resistors serving as a second voltage detecting node; and a first comparator for detecting a voltage of the second voltage detecting node becoming higher than that of the first voltage detecting node to output a power-on signal.

Abstract translation: 一种具有上电检测电路的半导体集成电路器件，其中所述通电检测电路包括：第一和第二电源端子，其间将提供外部电源电压; 第一二极管电路，具有串联连接在第一和第二电源端子之间的第一电阻器和第一二极管，第一电阻器和第一二极管之间的互连节点，用作第一电压检测节点; 具有第二和第三电阻器的第二二极管电路和串联连接在第一和第二电源端子之间的第二二极管，第二二极管的电流驱动能力大于第一二极管，第二和第三电阻器之间的互连节点用作 第二电压检测节点; 以及第一比较器，用于检测第二电压检测节点的电压变得高于第一电压检测节点的电压，以输出电源接通信号。

公开(公告)号：US20060092708A1

公开(公告)日：2006-05-04

申请号：US11305193

申请日：2005-12-19

Applicant: Koichi Kawai ,  Tomoharu Tanaka ,  Noboru Shibata

Inventor： Koichi Kawai ,  Tomoharu Tanaka ,  Noboru Shibata

IPC: G11C16/06

CPC classification number: G11C16/3468

Abstract: A semiconductor memory device includes: a plurality of cell array blocks in each of which a plurality of memory cells are arranged; address decode circuits for selecting memory cells in the cell array blocks; sense amplifier circuits for reading cell data of the cell array blocks; and a busy signal generation circuit for generating a busy signal to the chip external, wherein in a first read cycle selecting a first area in a first cell array block, cell data read operations for the first area of the first cell array block and a second area of a second cell array block are simultaneously executed, while the busy signal generation circuit generates a true busy signal, and then a read data output operation is executed for outputting the read out data of the first area held in the sense amplifier circuits to the chip external, and in a second read cycle selecting the second area in the second cell array block, after the busy signal generation circuit has output a dummy busy signal shorter in time length than the true busy signal without executing cell data read operation, a read data output operation is executed for outputting the read out data of the second area held in the sense amplifier circuits to the chip external.

Abstract translation: 半导体存储器件包括：多个单元阵列块，每个单元阵列块中布置有多个存储单元; 用于选择单元阵列块中的存储单元的地址解码电路; 用于读取单元阵列块的单元数据的读出放大器电路; 以及用于向芯片外部产生忙信号的忙信号产生电路，其中在第一读周期中选择第一单元阵列块中的第一区，对第一单元阵列块的第一区进行单元数据读操作， 同时执行第二单元阵列块的区域，而忙信号产生电路产生真正的忙信号，然后执行读数据输出操作，以将保持在读出放大器电路中的第一区域的读出数据输出到 芯片外部，并且在第二读取周期中选择第二单元阵列块中的第二区域，在忙信号产生电路在不执行单元数据读取操作的情况下输出比真实忙信号更短的时间长度的虚拟忙信号，读取 执行数据输出操作，以将保持在读出放大器电路中的第二区域的读出数据输出到芯片外部。

公开(公告)号：US20060077712A1

公开(公告)日：2006-04-13

申请号：US11289509

申请日：2005-11-30

Applicant: Tomoharu Tanaka ,  Khandker Quader ,  Hiroyuki Dohmae ,  Atsushi Inoue ,  Takeaki Sato

Inventor： Tomoharu Tanaka ,  Khandker Quader ,  Hiroyuki Dohmae ,  Atsushi Inoue ,  Takeaki Sato

IPC: G11C16/04 ,  G11C11/34

CPC classification number: G06K19/07732 ,  G11C7/1045 ,  G11C16/26 ,  G11C16/32

Abstract: Disclosed is a non-volatile semiconductor memory device comprising a plurality of non-volatile semiconductor memory cells, an interface making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circuit for controlling the non-volatile semiconductor memory cells, wherein the interface and the control circuit include a first read mode initialized via a first bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting (N+M)-byte (N is the n-th power of 2, n is positive integers) data via the interface, and a second read mode initialized via a second bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting K-byte (K is the k-th power of 2, k is positive integers) data via the interface.

Abstract translation: 公开了一种包括多个非易失性半导体存储单元的非易失性半导体存储器件，与外部器件进行数据交换以对非易失性半导体存储单元进行写/读数据的接口，以及用于 控制所述非易失性半导体存储单元，其中所述接口和所述控制电路包括经由第一自举初始化的第一读取模式，以从所述非易失性半导体存储单元读取数据，以连续输出（N + M）字节（N为 经由接口的n的n次幂，n是正整数）数据，以及经由第二引导来初始化的第二读取模式，以从非易失性半导体存储器单元读取用于连续输出K字节的数据（K是k 功率为2，k为正整数）数据。

公开(公告)号：US06977845B2

公开(公告)日：2005-12-20

申请号：US10856986

申请日：2004-06-01

Applicant: Koichi Kawai ,  Tomoharu Tanaka ,  Noboru Shibata

Inventor： Koichi Kawai ,  Tomoharu Tanaka ,  Noboru Shibata

IPC: G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/26 ,  G11C16/34 ,  H01L27/00

CPC classification number: G11C16/3468

Abstract: A semiconductor memory device includes: a plurality of cell array blocks in each of which a plurality of memory cells are arranged; address decode circuits for selecting memory cells in the cell array blocks; sense amplifier circuits for reading cell data of the cell array blocks; and a busy signal generation circuit for generating a busy signal to the chip external, wherein in a first read cycle selecting a first area in a first cell array block, cell data read operations for the first area of the first cell array block and a second area of a second cell array block are simultaneously executed, while the busy signal generation circuit generates a true busy signal, and then a read data output operation is executed for outputting the read out data of the first area held in the sense amplifier circuits to the chip external, and in a second read cycle selecting the second area in the second cell array block, after the busy signal generation circuit has output a dummy busy signal shorter in time length than the true busy signal without executing cell data read operation, a read data output operation is executed for outputting the read out data of the second area held in the sense amplifier circuits to the chip external.

公开(公告)号：US06925004B2

公开(公告)日：2005-08-02

申请号：US10689868

申请日：2003-10-20

Applicant: Noboru Shibata ,  Tomoharu Tanaka

Inventor： Noboru Shibata ,  Tomoharu Tanaka

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/12

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/12 ,  G11C2211/5642 ,  G11C2211/5648

Abstract: In the operation of writing the second page, the control circuit precharges the bit line in verifying data “2” in the memory cell when the DDC has data “1” in it after the data cache is set and does not precharge the bit line when the DDC has data “0” in it. As a result, when data “2” has been written into the memory cell, the bit line is at the intermediate potential, which raises the threshold voltage of the memory cell a little.