公开(公告)号：US20250072093A1

公开(公告)日：2025-02-27

申请号：US17925002

申请日：2022-11-07

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Zhifu LI ,  Guanghui LIU ,  Fei AI ,  Dewei SONG ,  Zhuang LI

IPC: H01L29/45 ,  H01L29/49 ,  H01L29/786

Abstract: A display panel is provided. The display panel includes a substrate and includes a first ohmic contact structure, a first boss, a second ohmic contact structure, a semiconductor structure, and a gate which are stacked on the substrate. The first boss includes at least one sidewall. By arranging the semiconductor structure on the sidewall of the first boss, a length of a channel can be shortened by using an existing technology, and a dimension of a thin film transistor can be reduced, so that an integration level of the thin film transistor in the display panel can be improved.

公开(公告)号：US12238996B2

公开(公告)日：2025-02-25

申请号：US18534537

申请日：2023-12-08

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Hyun Ae Park ,  Sun-Ja Kwon ,  Byung Sun Kim ,  Yang Wan Kim ,  Su Jin Lee ,  Jae Yong Lee

IPC: H10K59/131 ,  G09G3/3233 ,  H10K59/121 ,  H10K77/10 ,  H01L27/12 ,  H01L29/45 ,  H01L29/49 ,  H01L49/02 ,  H10K50/80 ,  H10K102/00

Abstract: A display device includes a substrate including a display area and a peripheral area disposed around the display area. The peripheral area includes a bending region and a contact region adjacent to the bending region. A first connection line includes a first portion disposed in the contact region, and a second portion disposed in both the bending region and the contact region, and including a first layer and a second layer. At least part of the second layer of the second portion overlaps the first layer of the second portion. In the contact region, the first layer of the second portion is electrically connected to the first portion, and the second layer of the second portion is electrically connected to the first layer of the second portion.

公开(公告)号：US12237392B2

公开(公告)日：2025-02-25

申请号：US17465127

申请日：2021-09-02

Applicant: ASM IP Holding B.V.

Inventor： Suvi Haukka ,  Michael Givens ,  Eric Shero ,  Jerry Winkler ,  Petri Räisänen ,  Timo Asikainen ,  Chiyu Zhu ,  Jaakko Anttila

IPC: H01L29/49 ,  C23C16/06 ,  C23C16/34 ,  C23C16/455 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L29/51

Abstract: A process for depositing titanium aluminum or tantalum aluminum thin films comprising nitrogen on a substrate in a reaction space can include at least one deposition cycle. The deposition cycle can include alternately and sequentially contacting the substrate with a vapor phase Ti or Ta precursor and a vapor phase Al precursor. At least one of the vapor phase Ti or Ta precursor and the vapor phase Al precursor may contact the substrate in the presence of a vapor phase nitrogen precursor.

公开(公告)号：US12237368B2

公开(公告)日：2025-02-25

申请号：US17980949

申请日：2022-11-04

Applicant: Adeia Semiconductor Solutions LLC

Inventor： Injo Ok ,  Balasubramanian Pranatharthiharan ,  Soon-Cheon Seo ,  Charan V. Surisetty

IPC: H01L29/06 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/764 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/532 ,  H01L23/535 ,  H01L27/088 ,  H01L29/49 ,  H01L21/32 ,  H01L29/161 ,  H01L29/40 ,  H01L29/417

Abstract: A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.

公开(公告)号：US20250063759A1

公开(公告)日：2025-02-20

申请号：US18938295

申请日：2024-11-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Chieh Wang ,  Sheng-Wei Yeh ,  Yueh-Ching Pai ,  Chi-Jen Yang

IPC: H01L29/78 ,  H01L21/768 ,  H01L23/532 ,  H01L27/088 ,  H01L29/16 ,  H01L29/49 ,  H01L29/66

Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.

公开(公告)号：US12230706B2

公开(公告)日：2025-02-18

申请号：US18102831

申请日：2023-01-30

Applicant: Infineon Technologies Austria AG

Inventor： Ingmar Neumann ,  Michael Hutzler ,  David Laforet ,  Roland Moennich ,  Thomas Ralf Siemieniec

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

Abstract: In an embodiment, a transistor device a semiconductor substrate having a main surface, and a cell field including a plurality of transistor cells of a power transistor. The cell field further includes: a body region of a second conductivity type; a source region of a first conductivity type on or in the body region, the first conductivity type opposing the second conductivity type; a gate trench in the main surface of the semiconductor substrate; a gate dielectric lining the gate trench; a metal gate electrode arranged in the gate trench on the gate dielectric; and an electrically insulating cap arranged on the metal gate electrode. A method of fabricating a gate of the transistor device is also described.

公开(公告)号：US12225790B2

公开(公告)日：2025-02-11

申请号：US17946043

申请日：2022-09-16

Applicant: Samsung Display Co., Ltd.

Inventor： Chun Gi You ,  Gwang Geun Lee

IPC: H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H10K59/121 ,  H10K59/124 ,  H10K59/131 ,  H10K50/842

Abstract: A display device includes: a substrate; a semiconductor layer; a gate electrode overlapping the semiconductor layer; a common voltage line disposed on a same layer as the gate electrode; a common voltage line anti-oxidation layer disposed on the common voltage line; an interlayer insulating layer; source and drain electrodes disposed on the interlayer insulating layer; and a common voltage applying electrode disposed on a same layer as the source electrode and the drain electrode. The common voltage applying electrode is connected to the common voltage line through a first contact hole formed in the interlayer insulating layer, the common voltage line anti-oxidation layer includes an opening overlapping the common voltage line, the interlayer insulating layer is disposed in the opening, a width of the opening is smaller than a width of the common voltage line, and the first contact hole is disposed in the opening in a plan view.

公开(公告)号：US20250046620A1

公开(公告)日：2025-02-06

申请号：US18279827

申请日：2022-04-26

Applicant: HITACHI HIGH-TECH CORPORATION

Inventor： Kenta NAKAJIMA ,  Toru ITO ,  Fumiyoshi OFUJI

IPC: H01L21/3213 ,  H01J37/32 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L29/49 ,  H01L29/51 ,  H10B41/20 ,  H10B43/20

Abstract: A plasma processing method for uniformly removing a processing target film in a lateral direction even when a depth of a trench is increased, in particular, a method for plasma-etching a tungsten film of a stacked film formed by alternately stacking an insulating film and the tungsten film. The method includes: a first depositing step of depositing a film; a first etching step of etching after the first depositing step; a second depositing step of depositing a film; a second etching step of etching using a mixed gas after the second depositing step; and a third etching step of etching after the second etching step, the second depositing step being performed after the first depositing step and the first etching step are repeated a predetermined number of times, and the second depositing step, the second etching step, and the third etching step are repeated a predetermined number of times.

公开(公告)号：US20250040233A1

公开(公告)日：2025-01-30

申请号：US18915263

申请日：2024-10-14

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng CHING ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

Abstract: A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.

公开(公告)号：US12211836B2

公开(公告)日：2025-01-28

申请号：US18215059

申请日：2023-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Wen Chang ,  Hong-Nien Lin ,  Chien-Hsing Lee ,  Chih-Sheng Chang ,  Ling-Yen Yeh ,  Wilman Tsai ,  Yee-Chia Yeo

IPC: H01L27/06 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H10B51/30

Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.