公开(公告)号：US12237328B2

公开(公告)日：2025-02-25

申请号：US18136641

申请日：2023-04-19

Applicant: Adeia Semiconductor Solutions LLC

Inventor： Kangguo Cheng ,  Balasubramanian Pranatharthiharan ,  Alexander Reznicek ,  Charan V. Surisetty

IPC: H01L27/088 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H10B12/00

Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.

公开(公告)号：US12237368B2

公开(公告)日：2025-02-25

申请号：US17980949

申请日：2022-11-04

Applicant: Adeia Semiconductor Solutions LLC

Inventor： Injo Ok ,  Balasubramanian Pranatharthiharan ,  Soon-Cheon Seo ,  Charan V. Surisetty

IPC: H01L29/06 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/764 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/532 ,  H01L23/535 ,  H01L27/088 ,  H01L29/49 ,  H01L21/32 ,  H01L29/161 ,  H01L29/40 ,  H01L29/417

Abstract: A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.