公开(公告)号：US20240362180A1

公开(公告)日：2024-10-31

申请号：US18647549

申请日：2024-04-26

申请人： Intel Corporation

发明人： Subramaniam Maiyuran ,  Shubra Marwaha ,  Ashutosh Garg ,  Supratim Pal ,  Jorge Parra ,  Chandra Gurram ,  Varghese George ,  Darin Starkey ,  Guei-Yuan Lueh

IPC分类号： G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

CPC分类号： G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

摘要： Graphics processors and graphics processing units having dot product accumulate instructions for a hybrid floating point format are disclosed. In one embodiment, a graphics multiprocessor comprises an instruction unit to dispatch instructions and a processing resource coupled to the instruction unit. The processing resource is configured to receive a dot product accumulate instruction from the instruction unit and to process the dot product accumulate instruction using a bfloat16 number (BF16) format.

公开(公告)号：US12131063B2

公开(公告)日：2024-10-29

申请号：US17219138

申请日：2021-03-31

申请人： Advanced Micro Devices, Inc.

发明人： Kevin M. Lepak

IPC分类号： G06F3/00 ,  G06F3/06 ,  G06F12/0882 ,  G06F12/1009

CPC分类号： G06F3/0659 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0679 ,  G06F12/0882 ,  G06F12/1009

摘要： Methods and apparatus offload tiered memories management. The method includes obtaining a pointer to a stored memory management structure associated with tiered memories, where the memory management structure includes a plurality of memory management entries and each memory management entry of the plurality of memory management entries includes information for a memory section in one of the tiered memories. In some instances, the method includes scanning at least a part of the plurality of memory management entries. In certain instances, the method includes generating a memory profile list, where the memory profile list includes a plurality of profile entries and each profile entry of the plurality of profile entries corresponding to a scanned memory management entry in the memory management structure.

公开(公告)号：US12130740B2

公开(公告)日：2024-10-29

申请号：US17712632

申请日：2022-04-04

申请人： Intel Corporation

发明人： Jason W. Brandt ,  Robert S. Chappell ,  Jesus Corbal ,  Edward T. Grochowski ,  Stephen H. Gunther ,  Buford M. Guy ,  Thomas R. Huff ,  Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Ronak Singhal ,  Seyed Yahya Sotoudeh ,  Bret L. Toll ,  Lihu Rappoport ,  David B. Papworth ,  James D. Allen

IPC分类号： G06F12/0831 ,  G06F9/30 ,  G06F9/38 ,  G06F12/1009 ,  G06F12/1027

CPC分类号： G06F12/0831 ,  G06F9/30043 ,  G06F9/384 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/621 ,  G06F2212/68

摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

公开(公告)号：US20240354262A1

公开(公告)日：2024-10-24

申请号：US18760305

申请日：2024-07-01

申请人： Microsoft Technology Licensing, LLC

发明人： Stefan SAROIU ,  Alastair WOLMAN ,  Lucian COJOCAR ,  Kevin Robert LOUGHLIN

IPC分类号： G06F12/14 ,  G06F12/0893 ,  G06F12/1009 ,  G06F21/55

CPC分类号： G06F12/1425 ,  G06F12/0893 ,  G06F12/1009 ,  G06F21/556 ,  G06F2212/1052

摘要： Aspects of the present disclosure relate to techniques for minimizing the effects of RowHammer and induced charge leakage. In examples, systems and methods for preventing access pattern attacks in random-access memory (RAM) are provided. In aspects, a data request associated with a page table may be determined to be a potential security risk and such potential security risk may be mitigated by randomly selecting a memory region from a subset of memory regions, copying data stored in a memory region associated with a page table entry in the page table to the second memory region, disassociating the second memory region from the subset of memory regions and associating the memory region associated with the page table to the second memory region, and updating the page table entry in the page table to refer to the second memory region.

公开(公告)号：US20240354258A1

公开(公告)日：2024-10-24

申请号：US18685135

申请日：2023-02-03

申请人： HANGZHOU ALICLOUD FEITIAN INFORMATION TECHNOLOGY CO., LTD.

发明人： Hao ZHENG

IPC分类号： G06F12/1009 ,  G06F12/0873

CPC分类号： G06F12/1009 ,  G06F12/0873 ,  G06F2212/657

摘要： Provided in the embodiments of the present specification are a memory scanning method and apparatus, wherein the method includes: determining a reserved memory scanning range at a preset time interval; scanning reserved memory to be scanned within the reserved memory scanning range and determining a current cold and hot state of the reserved memory to be scanned; and determining a target record table for the current cold and hot state of the reserved memory to be scanned according to the current cold and hot state of the reserved memory to be scanned and recording the current cold and hot state of the reserved memory to be scanned into the target record table.

公开(公告)号：US20240354257A1

公开(公告)日：2024-10-24

申请号：US18136096

申请日：2023-04-18

申请人： Google LLC

发明人： Prashanth Prakash ,  Jerome Charles Jean Glisse

IPC分类号： G06F12/1009 ,  G06F12/0817

CPC分类号： G06F12/1009 ,  G06F12/0822

摘要： Accessing information associated with a virtual memory address by receiving a virtual memory address, translating the virtual memory address into a nominal physical memory address, receiving the nominal physical memory address at a memory migrator, and using the memory migrator to determine an old physical memory address corresponding to the nominal physical memory address and access the information at the old physical memory address or a new physical memory address. The accessing operation may be performed as part of migrating the information from an old physical memory location corresponding the old physical memory address to a new physical memory location corresponding to the new physical memory address.

公开(公告)号：US20240330200A1

公开(公告)日：2024-10-03

申请号：US18732494

申请日：2024-06-03

申请人： SK Hynix NAND Product Solutions Corp. (dba Solidigm)

发明人： Zion KWOK

IPC分类号： G06F12/1009

CPC分类号： G06F12/1009

摘要： This application is directed to compressing a logical-to-physical (L2P) address indirection table in a memory system of an electronic device. The electronic device determines a plurality of physical addresses corresponding to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device identifies a set of most significant bits (MSBs) and a set of least significant bits (LSBs) of each of the plurality of physical addresses and determines a set of data bits based on a plurality of MSB sets including the set of MSBs of each of the plurality of physical addresses. The set of LSBs of each of the plurality of physical addresses and the set of data bits are stored jointly in the L2P address indirection table.

公开(公告)号：US20240320002A1

公开(公告)日：2024-09-26

申请号：US18375381

申请日：2023-09-29

申请人： Intel Corporation

发明人： Jay LAWLOR ,  David SHEFFIELD ,  Xiang ZOU ,  Michael KINNEY ,  Charles HOLTHAUS ,  Thomas TOLL ,  Salessawi Ferede YITBAREK ,  Andreas KLEEN ,  Keshavan TIRUVALLUR ,  Sarathy JAYAKUMAR ,  Ruiyu NI

IPC分类号： G06F9/30 ,  G06F9/48 ,  G06F12/02 ,  G06F12/1009

CPC分类号： G06F9/30043 ,  G06F9/4812 ,  G06F12/0238 ,  G06F12/1009

摘要： An apparatus and method for a more efficient system management mode. For example, one embodiment of a processor comprises: a plurality of cores, at least a first core of the plurality of cores to perform operations to cause the plurality of cores to enter into a system management mode (SMM), the operations comprising: allocating a memory region for a system management RAM (SMRAM); writing an SMRAM state save location to a first register; and generating a page table in the SMRAM, including mapping a virtual address space a physical address space.

公开(公告)号：US12099449B2

公开(公告)日：2024-09-24

申请号：US18048364

申请日：2022-10-20

申请人： Micron Technology, Inc.

发明人： Giuseppe Cariello ,  Jonathan S. Parry

IPC分类号： G06F12/1009

CPC分类号： G06F12/1009 ,  G06F2212/651 ,  G06F2212/7201

摘要： Methods, systems, and devices for compressed logical-to-physical mapping for sequentially stored data are described. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block address generated by a host device to physical addresses of the memory device. The memory device may determine whether all of the entries of a terminal logical-to-physical mapping table are consecutive physical addresses. In response to determining that all of the entries contain consecutive physical addresses, the memory device may store a starting physical address of the consecutive physical addresses as an entry in a higher-level table along with a flag indicating that the entry points directly to data in the memory device rather than pointing to a terminal logical-to-physical mapping table. The memory device may, for subsequent reads of data stored in one or more of the consecutive physical addresses, bypass the terminal table to read the data.

公开(公告)号：US20240311166A1

公开(公告)日：2024-09-19

申请号：US18538237

申请日：2023-12-13

申请人： Microsoft Technology Licensing, LLC

发明人： Bruce J. SHERWIN, JR. ,  Sai Ganesh RAMACHANDRAN

IPC分类号： G06F9/455 ,  G06F12/1009 ,  G06F16/14 ,  G06F16/17

CPC分类号： G06F9/45545 ,  G06F9/45558 ,  G06F12/1009 ,  G06F16/144 ,  G06F16/1734 ,  G06F2009/45575 ,  G06F2009/45591 ,  G06F2212/7201

摘要： Hot restart of a hypervisor by replacing a running first hypervisor by a second hypervisor with minimally perceptible downtime to guest partitions. A first hypervisor is executed on a computing system. The first hypervisor is configured to create one or more guest partitions. During the hot restart, a service partition is generated and initialized with a second hypervisor. At least a portion of runtime state of the first hypervisor is migrated and synchronized to the second hypervisor using inverse hypercalls. After the synchronization, the second hypervisor is devirtualized from the service partition to replace the first hypervisor. Devirtualizing includes transferring control of hardware resources from the first hypervisor to the second hypervisor, using the previously migrated and synchronized runtime state.