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    ENHANCED DURABILITY FOR SYSTEMS ON CHIP (SOCS)
    1.
    发明申请
    ENHANCED DURABILITY FOR SYSTEMS ON CHIP (SOCS) 有权

    公开(公告)号：US20220147455A1

    公开(公告)日：2022-05-12

    申请号：US17095229

    申请日：2020-11-11

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alexander J. Branover ,  Kevin M. Lepak ,  William A. Moyes

    IPC: G06F12/0804 ,  G06F13/16

    Abstract: A system-on-chip with runtime global push to persistence includes a data processor having a cache, an external memory interface, and a microsequencer. The external memory interface is coupled to the cache and is adapted to be coupled to an external memory. The cache provides data to the external memory interface for storage in the external memory. The microsequencer is coupled to the data processor. In response to a trigger signal, the microsequencer causes the cache to flush the data by sending the data to the external memory interface for transmission to the external memory.

    Home agent based cache transfer acceleration scheme
    3.
    发明授权
    Home agent based cache transfer acceleration scheme 有权

    公开(公告)号：US10776282B2

    公开(公告)日：2020-09-15

    申请号：US15844215

    申请日：2017-12-15

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Amit P. Apte ,  Ganesh Balakrishnan ,  Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak

    IPC: G06F12/128 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0891

    Abstract: Systems, apparatuses, and methods for implementing a speculative probe mechanism are disclosed. A system includes at least multiple processing nodes, a probe filter, and a coherent slave. The coherent slave includes an early probe cache to cache recent lookups to the probe filter. The early probe cache includes entries for regions of memory, wherein a region includes a plurality of cache lines. The coherent slave performs parallel lookups to the probe filter and the early probe cache responsive to receiving a memory request. An early probe is sent to a first processing node responsive to determining that a lookup to the early probe cache hits on a first entry identifying the first processing node as an owner of a first region targeted by the memory request and responsive to determining that a confidence indicator of the first entry is greater than a threshold.

    Tiered memory caching
    4.
    发明授权
    Tiered memory caching 有权

    公开(公告)号：US12189535B2

    公开(公告)日：2025-01-07

    申请号：US18091140

    申请日：2022-12-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Vydhyanathan Kalyanasundharam ,  Ganesh Balakrishnan ,  Kevin M. Lepak ,  Amit P. Apte

    IPC: G06F12/08 ,  G06F12/0897

    Abstract: The disclosed computer-implemented method includes locating, from a processor storage, a partial tag corresponding to a memory request for a line stored in a memory having a tiered memory cache and in response to a partial tag hit for the memory request, locating, from a partition of the tiered memory cache indicated by the partial tag, a full tag for the line. The method also includes fetching, in response to a full tag hit, the requested line from the partition of the tiered memory cache. Various other methods, systems, and computer-readable media are also disclosed.

    METHODS AND APPARATUS FOR OFFLOADING TIERED MEMORIES MANAGEMENT
    6.
    发明申请
    METHODS AND APPARATUS FOR OFFLOADING TIERED MEMORIES MANAGEMENT 有权

    公开(公告)号：US20220317925A1

    公开(公告)日：2022-10-06

    申请号：US17219138

    申请日：2021-03-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Kevin M. Lepak

    IPC: G06F3/06 ,  G06F12/0882 ,  G06F12/1009

    Abstract: Methods and apparatus offload tiered memories management. The method includes obtaining a pointer to a stored memory management structure associated with tiered memories, where the memory management structure includes a plurality of memory management entries and each memory management entry of the plurality of memory management entries includes information for a memory section in one of the tiered memories. In some instances, the method includes scanning at least a part of the plurality of memory management entries. In certain instances, the method includes generating a memory profile list, where the memory profile list includes a plurality of profile entries and each profile entry of the plurality of profile entries corresponding to a scanned memory management entry in the memory management structure.

    Region based split-directory scheme to adapt to large cache sizes
    7.
    发明授权
    Region based split-directory scheme to adapt to large cache sizes 有权

    公开(公告)号：US11314646B2

    公开(公告)日：2022-04-26

    申请号：US16919638

    申请日：2020-07-02

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Amit P. Apte ,  Ganesh Balakrishnan

    IPC: G06F12/0817

    Abstract: Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.

    Light-weight memory expansion in a coherent memory system
    8.
    发明授权
    Light-weight memory expansion in a coherent memory system 有权

    公开(公告)号：US11036658B2

    公开(公告)日：2021-06-15

    申请号：US16249649

    申请日：2019-01-16

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Vydhyanathan Kalyanasundharam ,  Philip Ng ,  Alexander J Branover ,  Kevin M. Lepak

    IPC: G06F13/16 ,  G06F9/38 ,  G06F9/50 ,  G06F9/48

    Abstract: Systems, methods, and port controller designs employ a light-weight memory protocol. A light-weight memory protocol controller is selectively coupled to a Cache Coherent Interconnect for Accelerators (CCIX) port. Over an on-chip interconnect fabric, the light-weight protocol controller receives memory access requests from a processor and, in response, transmits associated memory access requests to an external memory through the CCIX port using only a proper subset of CCIX protocol memory transactions types including non-cacheable transactions and non-snooping transactions. The light-weight memory protocol controller is selectively uncoupled from the CCIX port and a remote coherent slave controller is coupled in its place. The remote coherent slave controller receives memory access requests and, in response, transmits associated memory access requests to a memory module through the CCIX port using cacheable CCIX protocol memory transaction types.

    HOME AGENT BASED CACHE TRANSFER ACCELERATION SCHEME
    9.
    发明申请
    HOME AGENT BASED CACHE TRANSFER ACCELERATION SCHEME 有权

    公开(公告)号：US20210064545A1

    公开(公告)日：2021-03-04

    申请号：US17019999

    申请日：2020-09-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Amit P. Apte ,  Ganesh Balakrishnan ,  Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak

    IPC: G06F12/128 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0891

    Abstract: Systems, apparatuses, and methods for implementing a speculative probe mechanism are disclosed. A system includes at least multiple processing nodes, a probe filter, and a coherent slave. The coherent slave includes an early probe cache to cache recent lookups to the probe filter. The early probe cache includes entries for regions of memory, wherein a region includes a plurality of cache lines. The coherent slave performs parallel lookups to the probe filter and the early probe cache responsive to receiving a memory request. An early probe is sent to a first processing node responsive to determining that a lookup to the early probe cache hits on a first entry identifying the first processing node as an owner of a first region targeted by the memory request and responsive to determining that a confidence indicator of the first entry is greater than a threshold.

    Region based split-directory scheme to adapt to large cache sizes
    10.
    发明授权
    Region based split-directory scheme to adapt to large cache sizes 有权

    公开(公告)号：US12158845B2

    公开(公告)日：2024-12-03

    申请号：US17721809

    申请日：2022-04-15

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Amit P. Apte ,  Ganesh Balakrishnan

    IPC: G06F12/0817

    Abstract: Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.

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