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    Delta-sigma modulator having expanded fractional input range
    1.
    发明授权
    Delta-sigma modulator having expanded fractional input range 有权

    公开(公告)号：US10291239B1

    公开(公告)日：2019-05-14

    申请号：US16000698

    申请日：2018-06-05

    Applicant: Xilinx, Inc.

    Inventor： Zhaoyin D. Wu ,  Winson Lin ,  Parag Upadhyaya ,  Geoffrey Zhang ,  Kun-Yung Chang

    IPC: H03L7/08 ,  H03L7/197

    Abstract: An example apparatus includes an input circuit including a first adder and a first multiplier, the first adder configured to level-shift an input signal by an amount and the first multiplier configured to multiply output of the adder by a factor. The apparatus further includes a multi-stage noise shaping (MASH) circuit having an input coupled to the first multiplier. The apparatus further includes an output circuit including a second multiplier and a second adder, the second multiplier configured to multiply output of the MASH circuit by a reciprocal of the factor and the second adder configured to level-shift output of the second multiplier by an inverse of the amount.

    Clock and data recovery circuit having tunable fractional-N phase locked loop
    3.
    发明授权
    Clock and data recovery circuit having tunable fractional-N phase locked loop 有权

    公开(公告)号：US10224937B1

    公开(公告)日：2019-03-05

    申请号：US15959104

    申请日：2018-04-20

    Applicant: Xilinx, Inc.

    Inventor： Zhaoyin D. Wu ,  Geoffrey Zhang ,  Parag Upadhyaya ,  Kun-Yung Chang

    IPC: H03L7/08 ,  H04L7/00 ,  H04L1/00 ,  H03L7/197 ,  H03L7/099 ,  H04L7/033

    Abstract: An example clock and data recovery (CDR) circuit includes a phase interpolator, a fractional-N phase locked loop (PLL) configured to supply a clock signal to the phase interpolator, and a phase detector configured to generate a phase detect result signal in response to phase detection of data samples and crossing samples of a received signal, the data samples and the crossing samples being generated based on a data phase and a crossing phase, respectively, or a sampling clock supplied by a phase interpolator. The CDR circuit further includes a digital loop filter configured to generate a phase interpolator code for controlling the phase interpolator, the digital loop filter including a phase path and a frequency path. The CDR circuit further includes a control circuit configured to control the digital loop filter to disconnect the frequency path from the phase path and to connect the frequency path to a control input of the fractional-N PLL.

    RECONFIGURABLE FRACTIONAL-N FREQUENCY GENERATION FOR A PHASE-LOCKED LOOP
    4.
    发明申请
    RECONFIGURABLE FRACTIONAL-N FREQUENCY GENERATION FOR A PHASE-LOCKED LOOP 审中-公开
    用于相位锁定环路的可重构分段N频率生成

    公开(公告)号：US20160322979A1

    公开(公告)日：2016-11-03

    申请号：US14700695

    申请日：2015-04-30

    Applicant: Xilinx, Inc.

    Inventor： Parag Upadhyaya ,  Adebabay M. Bekele ,  Didem Z. Turker Melek ,  Zhaoyin D. Wu

    IPC: H03L7/095 ,  H04B1/50 ,  H03M3/00

    CPC classification number: H03L7/095 ,  H03L7/18 ,  H03L7/197 ,  H03L7/1974 ,  H03M3/30 ,  H04B1/50

    Abstract: In an example, a phase-locked loop (PLL) circuit includes an error detector operable to generate an error signal; an oscillator operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times a reference frequency; a frequency divider operable to divide the output frequency of the output signal to generate a feedback signal based on a divider control signal; a sigma-delta modulator (SDM) operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM responsive to an order select signal operable to select an order of the SDM; and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM.

    Abstract translation: 在一个示例中，锁相环（PLL）电路包括可操作以产生误差信号的误差检测器; 振荡器，其可操作以提供具有基于所述误差信号和频带选择信号的输出频率的输出信号，所述输出频率是频率乘数乘以参考频率; 分频器，用于将输出信号的输出频率除以基于分频器控制信号产生反馈信号; Σ-Δ调制器（SDM），可操作以基于表示所述倍频器的整数值和分数值的输入产生所述除法器控制信号，所述SDM响应于可操作以选择所述SDM的次序的订单选择信号; 以及状态机，其可操作以在获取状态下生成所述频带选择信号并设置所述SDM的顺序。

    Continuous time linear equalization (CTLE) adaptation algorithm enabling baud-rate clock data recovery(CDR) locked to center of eye
    6.
    发明授权
    Continuous time linear equalization (CTLE) adaptation algorithm enabling baud-rate clock data recovery(CDR) locked to center of eye 有权

    公开(公告)号：US10791009B1

    公开(公告)日：2020-09-29

    申请号：US16682806

    申请日：2019-11-13

    Applicant: Xilinx, Inc.

    Inventor： Zhaoyin D. Wu ,  Parag Upadhyaya

    IPC: H04L25/03 ,  H04L27/01 ,  H04L27/00 ,  H04L7/00

    Abstract: Apparatus and associated methods relate to adapting a continuous time linear equalization circuit with minimum mean square error baud-rate clock and data recovery circuit to be able to lock to the center or near center of an eye diagram. In an illustrative example, a circuit may include an inter-symbol interference (ISI) detector configured to receive data and error samples, a summing circuit coupled to the output of the ISI detector, a moving average filter configured to receive the output of the summing circuit and generate an average output, a voter configured to generate a vote in response to the average output and a predetermined threshold, and, an accumulator and code generator configured to generate a code signal in response to the generated vote. By introducing the moving average filter and the voter, a quicker way to lock to the center or near center of an eye diagram may be obtained.

    CHANNEL ADAPTIVE ADC-BASED RECEIVER
    8.
    发明申请
    CHANNEL ADAPTIVE ADC-BASED RECEIVER 有权
    通道自适应ADC基接收器

    公开(公告)号：US20160352557A1

    公开(公告)日：2016-12-01

    申请号：US14723171

    申请日：2015-05-27

    Applicant: Xilinx, Inc.

    Inventor： Yu Liao ,  Geoffrey Zhang ,  Hongtao Zhang ,  Kun-Yung Chang ,  Toan Pham ,  Zhaoyin D. Wu

    IPC: H04L27/38 ,  H04L25/03

    CPC classification number: H04L27/3809 ,  H04L25/03057 ,  H04L25/03885

    Abstract: A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving the equalized sampled for providing re-equalized samples; and a slicer coupled to the DFE block for slicing the re-equalized samples. A receiver adaptation block is coupled to the first signal processing block and the second signal processing block. The receiver adaptation block is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel.

    Abstract translation: 接收机一般涉及信道适配。 在该接收机中，第一信号处理块耦合到通信信道。 第一信号处理块包括：AGC块和CTLE块，用于接收用于提供模拟信号的调制信号; 用于将模拟信号转换为数字样本的ADC; 以及用于均衡数字样本以提供均衡样本的FFE块。 第二信号处理块包括：DFE块，用于接收用于提供重新均衡的采样的采样的均衡; 以及耦合到DFE块的限幅器，用于对重新平衡的样本进行切片。 接收机适配块耦合到第一信号处理块和第二信号处理块。 接收器适配块被配置用于提供AGC适配，CTLE适配和对通信信道的限幅器适配。

    Adaptive method to reduce training time of receivers
    9.
    发明授权
    Adaptive method to reduce training time of receivers 有权

    公开(公告)号：US10530561B1

    公开(公告)日：2020-01-07

    申请号：US16359921

    申请日：2019-03-20

    Applicant: Xilinx, Inc.

    Inventor： Zao Liu ,  Yang Liu ,  Zhaoyin D. Wu ,  Geoffrey Zhang ,  Yu Xu ,  Alan C. Wong

    IPC: H04L7/00 ,  H04L25/02 ,  H04L25/03

    Abstract: Apparatus and associated methods relate to using a high learning rate to speed up the training of a receiver and switching from a high learning rate to a low learning rate for fine tuning based on exponentially weighted moving average convergence. In an illustrative example, a selection circuit may switch the high learning rate to the low learning rate based on a comparison of a moving average difference en to a predetermined stability criteria T1 of the receiver. The moving average difference en may include an exponentially weighted moving average of a difference between two consecutive exponentially weighted moving averages of an operation parameter un of the signal communication channel. By using this method, the training time for the receiver may be advantageously reduced.

    Systems and methods for clock and data recovery
    10.
    发明授权
    Systems and methods for clock and data recovery 有权

    公开(公告)号：US10256968B1

    公开(公告)日：2019-04-09

    申请号：US15660141

    申请日：2017-07-26

    Applicant: Xilinx, Inc.

    Inventor： Zhaoyin D. Wu ,  Yu Xu ,  Winson Lin ,  Yohan Frans ,  Geoffrey Zhang

    IPC: H04L7/00 ,  H03L7/081 ,  H04L7/033

    Abstract: A clock and data recovery (CDR) circuit includes a phase detector, a digital loop filter, and a lock detector. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples. The plurality of samples are generated by sampling a received signal based on a sampling clock a sampling clock provided by a phase interpolator. The digital loop filter includes a phase path and a frequency path for providing a phase path correction signal and a frequency path correction signal based on the phase detect result signal respectively. A phase interpolator code generator generates a phase interpolator code for controlling the phase interpolator based on the phase path correction signal and frequency path correction signal. The lock detector generates a lock condition signal based on the frequency path correction signal, the lock condition signal indicating a lock condition of the CDR circuit.

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