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公开(公告)号：US20190164579A1
公开(公告)日：2019-05-30
申请号：US16263184
申请日：2019-01-31
摘要： An integrated circuit device is disclosed that includes an sense amplifier having first and second input terminals, a compensation network including a first compensation circuit coupled to the first input terminal of the sense amplifier and a second compensation circuit coupled to the second input terminal of the sense amplifier, and a latch circuit operable to selectively enable either one of the first and second compensation circuits, but not both of the first and second compensation circuits simultaneously.
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公开(公告)号：US10062443B2
公开(公告)日：2018-08-28
申请号：US15709498
申请日：2017-09-20
CPC分类号： G11C17/08 , G11C7/18 , G11C16/0433 , G11C16/26 , G11C16/30
摘要： A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.
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公开(公告)号：US09202859B1
公开(公告)日：2015-12-01
申请号：US14287434
申请日：2014-05-27
IPC分类号： H01L27/06 , H01L49/02 , H01L29/06 , H01L21/762 , H01L21/3105 , H01L21/265 , H01L21/324 , H01L21/8234
CPC分类号： H01L28/20 , H01L21/26513 , H01L21/31053 , H01L21/324 , H01L21/76224 , H01L21/823418 , H01L27/0802 , H01L29/0649 , H01L29/66166 , H01L29/8605
摘要： An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.
摘要翻译： 包含阱电阻器的集成电路在阱电阻器中具有STI场氧化物和电阻器虚设有源区。 STI沟槽被蚀刻并填充沟槽填充电介质材料。 通过CMP工艺从有源区域上去除沟槽填充介电材料，在STI沟槽中留下STI场氧化物。 随后，将掺杂剂注入到阱电阻器区域中的衬底中以形成阱电阻器。 包含多晶硅电阻器的集成电路在多晶硅电阻器的区域中具有STI场氧化物和电阻器虚设有源区域。 通过CMP工艺形成并平坦化多晶硅层。 在CMP平坦化的多晶硅层上形成多晶硅蚀刻掩模以限定多晶硅电阻。 多晶硅蚀刻工艺在由多晶硅蚀刻掩模暴露的区域中去除多晶硅，留下多晶硅电阻器。
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公开(公告)号：US09799408B2
公开(公告)日：2017-10-24
申请号：US15050678
申请日：2016-02-23
CPC分类号： G11C17/08 , G11C7/18 , G11C16/0433 , G11C16/26 , G11C16/30
摘要： A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.
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公开(公告)号：US20160056227A1
公开(公告)日：2016-02-25
申请号：US14920366
申请日：2015-10-22
CPC分类号： H01L28/20 , H01L21/26513 , H01L21/31053 , H01L21/324 , H01L21/76224 , H01L21/823418 , H01L27/0802 , H01L29/0649 , H01L29/66166 , H01L29/8605
摘要： An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.
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公开(公告)号：US20180366205A1
公开(公告)日：2018-12-20
申请号：US16112402
申请日：2018-08-24
摘要： A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.
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公开(公告)号：US20170243659A1
公开(公告)日：2017-08-24
申请号：US15050678
申请日：2016-02-23
IPC分类号： G11C17/08
CPC分类号： G11C17/08 , G11C7/18 , G11C16/0433 , G11C16/26 , G11C16/30
摘要： A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.
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公开(公告)号：US09236107B1
公开(公告)日：2016-01-12
申请号：US14324048
申请日：2014-07-03
CPC分类号： G11C11/221 , G11C5/06 , G11C11/22 , G11C11/2253 , G11C11/2257 , G11C11/2273 , G11C11/2275 , G11C11/2293 , G11C11/5657 , G11C13/004
摘要： A system on chip (SoC) may have an array ferroelectric bit cells. The array may include a plurality of bit cells organized into a plurality of rows and columns. A set of word lines is configured such that one of the plurality of word lines is connected to each bit cell in a row of bit cells. A set of column oriented platelines is provided, wherein each column of bit cells has one of the plurality of platelines connected to each bit cell in the column of bit cells. A set of bitlines is provided, wherein each column of bit cells has one of the plurality of bitlines connected to each bit cell in the column of bit cells. Multiplexors may be used to allow one plateline drivers, bitline drivers, and sense amps to be shared between multiple platelines and bitlines.
摘要翻译： 片上系统（SoC）可以具有阵列铁电位单元。 阵列可以包括组织成多个行和列的多个位单元。 一组字线被配置为使得多个字线中的一个字连接到一行位单元中的每个位单元。 提供了一组以列为单位的行列，其中每列位单元具有连接到位单元列中的每个位单元的多个板之一。 提供了一组位线，其中每列位单元具有连接到位单元列中的每个位单元的多个位线之一。 多路复用器可以用于允许一个平台驱动器，位线驱动器和感测放大器在多个板条和位线之间共享。
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公开(公告)号：US10199078B2
公开(公告)日：2019-02-05
申请号：US15585332
申请日：2017-05-03
摘要： An amplifier circuit is disclosed having an amplifier with first and second input terminals. The amplifier circuit includes a first compensation capacitor coupled to the first input terminal and having a first capacitance, a second compensation capacitor coupled to the second input terminal and having a second capacitance, a first transistor coupled between the first compensation capacitor and a reference voltage and having a gate terminal that receives a first control signal, and a second transistor coupled between the second compensation capacitor and the reference voltage and having a gate terminal for receiving a second control signal. The amplifier circuit includes a programmable latch circuit arranged to provide the first and second control signals, wherein the first and second transistors are of the same conductivity type, and the first control signal and the second control signal are complementary signals with respect to each other.
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公开(公告)号：US09704554B2
公开(公告)日：2017-07-11
申请号：US14834754
申请日：2015-08-25
CPC分类号： G11C7/065 , G11C7/10 , G11C11/221 , G11C11/223 , G11C11/2273 , H03F1/0205 , H03F3/16
摘要： An amplifier circuit is disclosed having an amplifier with first and second input terminals coupled to receive an input signal. A first compensation circuit is coupled to the first input terminal, and a second compensation circuit is coupled to the second input terminal. A programmable latch circuit is arranged to select one of the first and second compensation circuits.
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