公开(公告)号：US11574900B2

公开(公告)日：2023-02-07

申请号：US16910658

申请日：2020-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Liang Chen ,  Shun Li Chen ,  Li-Chun Tien ,  Ting Yu Chen ,  Hui-Zhong Zhuang

IPC: H01L27/02 ,  G06F30/392 ,  H01L27/092

Abstract: A method includes generating a layout diagram of a cell of an integrated circuit (IC), and storing the generated layout diagram on a non-transitory computer-readable medium. In the generating the layout diagram of the cell, a first active region is arranged inside a boundary of the cell. The first active region extends along a first direction. At least one gate region is arranged inside the boundary. The at least one gate region extends across the first active region along a second direction transverse to the first direction. A first conductive region is arranged to overlap the first active region and a first edge of the boundary. The first conductive region is configured to form an electrical connection to the first active region.

公开(公告)号：US09478533B2

公开(公告)日：2016-10-25

申请号：US14714369

申请日：2015-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Yu Ma ,  Bo-Ting Chen ,  Ting Yu Chen ,  Kuo-Ji Chen ,  Li-Chun Tien

IPC: H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/118 ,  H01L49/02

CPC classification number: H01L27/0288 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0629 ,  H01L27/11807 ,  H01L28/20 ,  H01L28/24

Abstract: An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.

公开(公告)号：US09035393B2

公开(公告)日：2015-05-19

申请号：US13779783

申请日：2013-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Yu Ma ,  Bo-Ting Chen ,  Ting Yu Chen ,  Kuo-Ji Chen ,  Li-Chun Tien

IPC: H01L27/02 ,  H01L27/06 ,  H01L27/118 ,  H01L49/02

CPC classification number: H01L27/0288 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0629 ,  H01L27/11807 ,  H01L28/20 ,  H01L28/24

Abstract: An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.

Abstract translation: 集成电路包括半导体器件层，其包括在栅电极线之间具有固定栅电极间距的标准单元配置和在标准单元配置的固定栅电极间距之间由金属形成的电阻。 在一个实施例中，集成电路可以是具有由金属形成的电阻器的交叉域标准单元的充电器件模型（CDM）静电放电（ESD）保护电路。 制造集成电路的方法包括：形成由栅电极间距分开的多个栅极电极线，以形成芯标准电池器件，在栅电极间距内施加至少第一金属层以形成电阻器的一部分，以及 施加至少第二金属层以耦合到第一金属层以形成电阻器的另一部分。

公开(公告)号：US12125840B2

公开(公告)日：2024-10-22

申请号：US18156605

申请日：2023-01-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Liang Chen ,  Shun Li Chen ,  Li-Chun Tien ,  Ting Yu Chen ,  Hui-Zhong Zhuang

IPC: H01L27/02 ,  G06F30/392 ,  H01L27/092

CPC classification number: H01L27/0207 ,  G06F30/392 ,  H01L27/092

Abstract: A non-transitory computer-readable medium contains thereon a cell library. The cell library includes a plurality of cells configured to be placed in a layout diagram of an integrated circuit (IC). Each cell among the plurality of cells includes a first active region inside a boundary of the cell. The first active region extends along a first direction. At least one gate region is inside the boundary. The at least one gate region extends across the first active region along a second direction transverse to the first direction. A first conductive region overlaps the first active region and a first edge of the boundary. The first conductive region is configured to form an electrical connection to the first active region. The plurality of cells includes at least one cell a width of which in the first direction is equal to one gate region pitch between adjacent gate regions of the IC.

公开(公告)号：US12094880B2

公开(公告)日：2024-09-17

申请号：US18168065

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ali Keshavarzi ,  Ta-Pen Guo ,  Shu-Hui Sung ,  Hsiang-Jen Tseng ,  Shyue-Shyh Lin ,  Lee-Chung Lu ,  Chung-Cheng Wu ,  Li-Chun Tien ,  Jung-Chan Yang ,  Ting Yu Chen ,  Min Cao ,  Yung-Chin Hou

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/4238 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

公开(公告)号：US09405879B2

公开(公告)日：2016-08-02

申请号：US14231858

申请日：2014-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Sen Wang ,  Ting Yu Chen ,  Ken-Hsien Hsieh ,  Ming-Yi Lin ,  Chen-Hung Lu

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5081 ,  G06F9/455 ,  G06F17/5068 ,  G06F17/5072

Abstract: Some embodiments relate to a method of hierarchical layout design, comprising forming a layout of an integrated circuit (IC) according to a design rule that specifies a minimum design rule distance between a neighboring layout features within the IC. Forming the layout comprises forming first and second standard cells having first and second layout features, respectively, that about one-another so that a distance between the first and second layout features is less than the minimum design rule distance. The method further comprises configuring design rule checking (DRC) to ignore this fail. Instead, the layout is modified with an automated layout tool by merging the first and second layout features, or by removing a portion of the first or second layout feature to increase the distance between the first and second layout features to be greater than or equal to the minimum distance.

Abstract translation: 一些实施例涉及分层布局设计的方法，包括根据规定IC内的相邻布局特征之间的最小设计规则距离的设计规则来形成集成电路（IC）的布局。 形成布局包括分别形成具有第一和第二布局特征的第一和第二标准单元，使得第一和第二布局特征之间的距离小于最小设计规则距离。 该方法还包括配置设计规则检查（DRC）以忽略该失败。 相反，通过合并第一和第二布局特征，或者通过移除第一或第二布局特征的一部分来增加第一和第二布局特征之间的距离来大于或等于 最小距离。

公开(公告)号：US09087170B2

公开(公告)日：2015-07-21

申请号：US14011790

申请日：2013-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiung Hsu ,  Yuan-Te Hou ,  Li-Chun Tien ,  Hui-Zhong Zhuang ,  Fang-Yu Fan ,  Wen-Hao Chen ,  Ting Yu Chen

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068

Abstract: A method includes comparing one or more cells to a selection guideline and storing the cells that meet the selection guideline in a non-transient computer readable storage medium to create the cell library based on the comparing. The selection guideline identifies a suitable position of a boundary pin within a cell.

Abstract translation: 一种方法包括将一个或多个单元与选择指南进行比较，并将满足选择准则的单元存储在非瞬态计算机可读存储介质中，以基于该比较创建单元库。 选择指南确定单元格内边界引脚的合适位置。

公开(公告)号：US09026971B1

公开(公告)日：2015-05-05

申请号：US14148898

申请日：2014-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Lin Ho ,  Chin-Chang Hsu ,  Hung Lung Lin ,  Wen-Ju Yang ,  Yi-Kan Cheng ,  Tsong-Hua Ou ,  Wen-Li Cheng ,  Ken-Hsien Hsieh ,  Ching Hsiang Chang ,  Ting Yu Chen ,  Li-Chun Tien

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F7/70466 ,  G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

Abstract: The present disclosure relates to a method and apparatus for forming a multiple patterning lithograph (MPL) compliant integrated circuit layout by operating a construction validation check on unassembled IC cells to enforce design restrictions that prevent MPL conflicts after assembly. In some embodiments, the method is performed by generating a plurality of unassembled integrated circuit (IC) cells having a multiple patterning design layer. A construction validation check is performed on the unassembled IC cells to identify violating IC cells having shapes disposed in patterns comprising potential multiple patterning coloring conflicts. Design shapes within a violating IC cell are adjusted to achieve a plurality of violation free IC cells. The plurality of violation free IC cells are then assembled to form an MPL compliant IC layout. Since the MPL compliant IC layout is free of coloring conflicts, a decomposition algorithm can be operated without performing a post assembly color conflict check.

Abstract translation: 本发明涉及一种用于通过对未组装的IC单元进行构造验证检查以形成在组装之后防止MPL冲突的设计限制来形成多重图案化平版印刷术（MPL）兼容集成电路布局的方法和装置。 在一些实施例中，该方法通过产生具有多个图案化设计层的多个未组装的集成电路（IC）单元来执行。 在未组装的IC细胞上进行结构验证检查，以识别具有以包含潜在的多个图案化着色冲突的图案布置的形状的违反IC细胞。 调整违规IC单元内的设计形状，以实现多个无冲突的IC单元。 然后组合多个违规免费IC电池以形成符合MPL的IC布局。 由于MPL兼容IC布局没有着色冲突，因此可以在不执行后期组合颜色冲突检查的情况下操作分解算法。

公开(公告)号：US11581314B2

公开(公告)日：2023-02-14

申请号：US16723939

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ali Keshavarzi ,  Ta-Pen Guo ,  Shu-Hui Sung ,  Hsiang-Jen Tseng ,  Shyue-Shyh Lin ,  Lee-Chung Lu ,  Chung-Cheng Wu ,  Li-Chun Tien ,  Jung-Chan Yang ,  Ting Yu Chen ,  Min Cao ,  Yung-Chin Hou

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.