公开(公告)号：US20230386834A1

公开(公告)日：2023-11-30

申请号：US18447869

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Kai YANG ,  Yu-Tien SHEN ,  Hsiang-Ming CHANG ,  Chun-Yen CHANG ,  Ya-Hui CHANG ,  Wei-Ting CHIEN ,  Chia-Cheng CHEN ,  Liang-Yin CHEN

IPC: H01L21/027 ,  H01L21/311 ,  G03F7/00 ,  H01L21/3115 ,  H01L21/768

CPC classification number: H01L21/0273 ,  H01L21/31144 ,  G03F7/70058 ,  H01L21/31155 ,  H01L21/76877

Abstract: A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.

公开(公告)号：US20190305107A1

公开(公告)日：2019-10-03

申请号：US15939389

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju CHEN ,  Su-Hao LIU ,  Chun-Hao KUNG ,  Liang-Yin CHEN ,  Huicheng CHANG ,  Kei-Wei CHEN ,  Hui-Chi HUANG ,  Kao-Feng LIAO ,  Chih-Hung CHEN ,  Jie-Huang HUANG ,  Lun-Kuang TAN ,  Wei-Ming YOU

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a dielectric layer, a contact plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The dielectric layer is positioned over the gate structure and the source/drain structure. The contact plug is positioned passing through the dielectric layer. The contact plug includes a first metal compound including one of group III elements, group IV elements, group V elements or a combination thereof.

公开(公告)号：US20190165099A1

公开(公告)日：2019-05-30

申请号：US15825533

申请日：2017-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng CHEN ,  Liang-Yin CHEN

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/45 ,  H01L21/02 ,  H01L21/223 ,  H01L21/324 ,  H01L29/66

Abstract: Embodiments disclosed herein relate generally to forming a source/drain region with a high surface dopant concentration at an upper surface of the source/drain region, to which a conductive feature may be formed. In an embodiment, a structure includes an active area on a substrate, a dielectric layer over the active area, and a conductive feature through the dielectric layer to the active area. The active area includes a source/drain region. The source/drain region includes a surface dopant region at an upper surface of the source/drain region, and includes a remainder portion of the source/drain region having a source/drain dopant concentration. The surface dopant region includes a peak dopant concentration proximate the upper surface of the source/drain region. The peak dopant concentration is at least an order of magnitude greater than the source/drain dopant concentration. The conductive feature contacts the source/drain region at the upper surface of the source/drain region.

公开(公告)号：US20190027473A1

公开(公告)日：2019-01-24

申请号：US15652719

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng CHEN ,  Chia-Ling CHAN ,  Liang-Yin CHEN ,  Huicheng CHANG

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a gate structure and a source/drain feature. The gate structure is positioned over a fin structure. The source/drain feature is positioned adjacent to the gate structure. A portion of the source/drain feature embedded in the fin structure has an upper sidewall portion adjacent to a top surface of the fin structure and a lower sidewall portion below the upper sidewall portion. A first curve radius of the upper sidewall portion is different from a second curve radius of the lower sidewall portion in a cross-sectional view substantially along the longitudinal direction of the fin structure.

公开(公告)号：US20250113551A1

公开(公告)日：2025-04-03

申请号：US18404785

申请日：2024-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng CHEN ,  Sih-Jie LIU ,  Liang-Yin CHEN ,  Chi On CHUI

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A method includes: forming a stack of nanostructures over a substrate; forming a source/drain opening adjacent the stack of nanostructures; forming a semiconductor layer in the source/drain opening; forming an amorphous semiconductor layer by performing an ion implantation on the semiconductor layer; and forming a recrystallized source/drain by annealing the amorphous semiconductor layer.

公开(公告)号：US20210096473A1

公开(公告)日：2021-04-01

申请号：US16587710

申请日：2019-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun LIU ,  Huicheng CHANG ,  Chia-Cheng CHEN ,  Jyu-Horng SHIEH ,  Liang-Yin CHEN ,  Shu-Huei SUEN ,  Wei-Liang LIN ,  Ya Hui CHANG ,  Yi-Nien SU ,  Yung-Sung YEN ,  Chia-Fong CHANG ,  Ya-Wen YEH ,  Yu-Tien SHEN

IPC: G03F7/20 ,  H01L21/027

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

公开(公告)号：US20200343242A1

公开(公告)日：2020-10-29

申请号：US16924541

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng CHEN ,  Chia-Ling CHAN ,  Liang-Yin CHEN ,  Huicheng CHANG

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: A method for forming a semiconductor structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes depositing a dopant source layer over the gate structure. The method also includes driving dopants of the dopant source layer into the fin structure. The method also includes removing the dopant source layer. The method also includes annealing the dopants in the fin structure to form a doped region. The method also includes etching the doped region and the fin structure below the doped region to form a recess. The method also includes growing a source/drain feature in the recess.

公开(公告)号：US20190157148A1

公开(公告)日：2019-05-23

申请号：US16021216

申请日：2018-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Po HSIEH ,  Su-Hao LIU ,  Hong-Chih LIU ,  Jing-Huei HUANG ,  Jie-Huang HUANG ,  Lun-Kuang TAN ,  Huicheng CHANG ,  Liang-Yin CHEN ,  Kuo-Ju CHEN

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a first contact plug and a first via plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The first contact plug is positioned over the source/drain structure. The first via plug is positioned over the first contact plug. The first via plug includes a first group IV element.

公开(公告)号：US20200266299A1

公开(公告)日：2020-08-20

申请号：US16869819

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng CHEN ,  Su-Hao LIU ,  Kuo-Ju CHEN ,  Liang-Yin CHEN

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L21/223

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an epitaxial structure over a semiconductor substrate. The method also includes generating and applying plasma on an entire exposed surface of the epitaxial structure to form a modified region in the epitaxial structure. The plasma is directly applied on the source/drain structure without being filtered out, and the plasma includes ions with different charges. The method further includes forming a metal layer on the modified region and heating the metal layer and the modified region to form a metal-semiconductor compound region.

公开(公告)号：US20220102139A1

公开(公告)日：2022-03-31

申请号：US17353400

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Kai YANG ,  Yu-Tien SHEN ,  Hsiang-Ming CHANG ,  Chun-Yen CHANG ,  Ya-Hui CHANG ,  Wei-Ting CHIEN ,  Chia-Cheng CHEN ,  Liang-Yin CHEN

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3115 ,  G03F7/20

Abstract: A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.