公开(公告)号：US11967504B2

公开(公告)日：2024-04-23

申请号：US17532204

申请日：2021-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Jia-Ming Lin ,  Kun-Yu Lee ,  Chi On Chui

IPC: H01L21/02

CPC classification number: H01L21/02603 ,  H01L21/02208 ,  H01L21/02271 ,  H01L21/0262

Abstract: A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

公开(公告)号：US11715762B2

公开(公告)日：2023-08-01

申请号：US17220335

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Jia-Ming Lin ,  Chi On Chui

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/265

CPC classification number: H01L29/0673 ,  H01L21/2654 ,  H01L27/0924

Abstract: In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.

公开(公告)号：US20230231037A1

公开(公告)日：2023-07-20

申请号：US18123596

申请日：2023-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Fan ,  Tsung-Han Shen ,  Jia-Ming Lin ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/6681 ,  H01L21/02274 ,  H01L21/823431 ,  H01L29/6656 ,  H01L29/7851 ,  H01L29/66545

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

公开(公告)号：US09824943B2

公开(公告)日：2017-11-21

申请号：US15082399

申请日：2016-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Ming Lin ,  Wei-Ken Lin ,  Shiu-Ko Jangjian ,  Chun-Che Lin

IPC: H01L21/762 ,  H01L21/66 ,  H01L21/3115 ,  H01L29/78

CPC classification number: H01L22/26 ,  H01L21/31105 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L22/12 ,  H01L29/7846 ,  H01L29/785

Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.

公开(公告)号：US11610982B2

公开(公告)日：2023-03-21

申请号：US17140897

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Fan ,  Tsung-Han Shen ,  Jia-Ming Lin ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/8234

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

公开(公告)号：US20240371981A1

公开(公告)日：2024-11-07

申请号：US18775706

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Fan ,  Tsung-Han Shen ,  Jia-Ming Lin ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

公开(公告)号：US20240249938A1

公开(公告)日：2024-07-25

申请号：US18599871

申请日：2024-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Jia-Ming Lin ,  Kun-Yu Lee ,  Chi On Chui

IPC: H01L21/02

CPC classification number: H01L21/02603 ,  H01L21/02208 ,  H01L21/02271 ,  H01L21/0262

Abstract: A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

公开(公告)号：US10861701B2

公开(公告)日：2020-12-08

申请号：US14754427

申请日：2015-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Ming Lin ,  Shiu-Ko Jangjian ,  Chun-Che Lin

IPC: H01L29/423 ,  H01L29/40 ,  H01L21/285 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L21/768

Abstract: A semiconductor device includes a substrate, at least one layer, a metal adhesive, and a metal structure. The layer is disposed on the substrate. The layer has an opening, and the opening has a bottom surface and at least one sidewall. The metal adhesive is disposed on the bottom surface of the opening while leaving at least a portion of the sidewall of the opening exposed. The metal structure is disposed in the opening and on the metal adhesive.

公开(公告)号：US10854713B2

公开(公告)日：2020-12-01

申请号：US15865072

申请日：2018-01-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Ming Lin ,  Shiu-Ko Jangjian ,  Chun-Che Lin ,  Ying-Lang Wang ,  Wei-Ken Lin ,  Chuan-Pu Liu

IPC: H01L21/3105 ,  H01L21/314 ,  H01L21/324 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/12 ,  H01L21/84

Abstract: A method includes forming a flowable dielectric layer in a trench of a substrate; curing the flowable dielectric layer; and annealing the cured flowable dielectric layer to form an insulation structure and a liner layer. The insulation structure is formed in the trench, the liner layer is formed between the insulation structure and the substrate, and the liner layer includes nitrogen.

公开(公告)号：US12218199B2

公开(公告)日：2025-02-04

申请号：US18333981

申请日：2023-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Jia-Ming Lin ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/265 ,  H01L27/092

Abstract: In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.