公开(公告)号：US20200043792A1

公开(公告)日：2020-02-06

申请号：US16147896

申请日：2018-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hung Chen ,  Chih-Hung Hsieh ,  Jhon-Jhy Liaw

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/36 ,  H01L29/06 ,  H01L27/088 ,  H01L29/10 ,  H01L21/762 ,  H01L27/11 ,  H01L29/66 ,  H01L29/165

Abstract: A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.

公开(公告)号：US09900471B2

公开(公告)日：2018-02-20

申请号：US15149175

申请日：2016-05-08

Applicant: GLOBAL UNICHIP CORPORATION ,  TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hung Chen ,  Cheng-Ta Lee

IPC: G06F9/00 ,  H04N1/60 ,  G06K9/62

CPC classification number: H04N1/60 ,  G06K9/6202 ,  H04N1/6086

Abstract: An image correction system includes a storage device and a processor. The storage device is configured to store multiple reference patterns corresponding to different color temperatures. The processor is configured to execute operations of receiving an input image and correspondingly transforming the input image into multiple input gamut points; generating an input pattern according to distribution of the input gamut points, in which the input gamut points are surrounded by the input pattern; comparing the input pattern with the reference patterns to generate a comparison result; and estimating out a color temperature corresponding to the input image according to the comparison result so as to correct the input image.

公开(公告)号：US10090327B2

公开(公告)日：2018-10-02

申请号：US14158430

申请日：2014-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Keng-Yu Chen ,  Wei-Kung Tsai ,  Kuan-Chi Tsai ,  Tsung-Yu Yang ,  Chung-Long Chang ,  Chun-Hung Chen ,  Chih-Ping Chao

IPC: H01L27/12 ,  H01L27/06 ,  H01L21/306 ,  H01L21/311 ,  H01L21/28 ,  H01L23/66 ,  H01L21/762 ,  H01L21/02 ,  H01L49/02 ,  H01L21/84 ,  H01L21/763 ,  H01L23/522

Abstract: Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a buried oxide layer formed over the substrate. An interface layer is formed between the substrate and the buried oxide layer. The semiconductor device structure also includes a silicon layer formed over the buried oxide layer; and a polysilicon layer formed over the substrate and in a deep trench. The polysilicon layer extends through the silicon layer, the buried oxide layer and the interface layer.

公开(公告)号：US09589831B2

公开(公告)日：2017-03-07

申请号：US14971031

申请日：2015-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Kuo-Yu Cheng ,  Keng-Yu Chen ,  Wei-Kung Tsai ,  Kuan-Chi Tsai ,  Tsung-Yu Yang ,  Chung-Long Chang ,  Chun-Hung Chen ,  Chih-Ping Chao

IPC: H01L27/12 ,  H01L21/306 ,  H01L21/762 ,  H01L21/84

CPC classification number: H01L21/76283 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203

Abstract: A method for forming a radio frequency area of an integrated circuit are provided. The method includes forming a buried oxide layer over a substrate, and an interface layer is formed between the substrate and the buried oxide layer. The method also includes etching through the buried oxide layer and the interface layer to form a deep trench, and a bottom surface of the deep trench is level with a bottom surface of the interface layer. The method further includes forming an implant region directly below the deep trench and forming an interlayer dielectric layer in the deep trench.

Abstract translation: 提供了一种用于形成集成电路的射频区域的方法。 该方法包括在衬底上形成掩埋氧化物层，并且在衬底和掩埋氧化物层之间形成界面层。 该方法还包括通过掩埋氧化物层和界面层蚀刻以形成深沟槽，并且深沟槽的底表面与界面层的底表面平齐。 该方法还包括在深沟槽的正下方形成植入区域，并在深沟槽中形成层间电介质层。

公开(公告)号：US09230988B2

公开(公告)日：2016-01-05

申请号：US14068353

申请日：2013-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Keng-Yu Chen ,  Wei-Kung Tsai ,  Kuan-Chi Tsai ,  Tsung-Yu Yang ,  Chung-Long Chang ,  Chun-Hung Chen ,  Chih-Ping Chao

IPC: H01L27/12 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203

Abstract: Embodiments of mechanisms of forming a radio frequency area of an integrated circuit are provided. The radio frequency area of an integrated circuit structure includes a substrate, a buried oxide layer formed over the substrate, and an interface layer formed between the substrate and the buried oxide layer. The radio frequency area of an integrated circuit structure also includes a silicon layer formed over the buried oxide layer and an interlayer dielectric layer formed in a deep trench. The radio frequency area of an integrated circuit structure further includes the interlayer dielectric layer extending through the silicon layer, the buried oxide layer and the interface layer. The radio frequency area of an integrated circuit structure includes an implant region formed below the interlayer dielectric layer in the deep trench and a polysilicon layer formed below the implant region.

Abstract translation: 提供了形成集成电路的射频区域的机构的实施例。 集成电路结构的射频区域包括衬底，在衬底上形成的掩埋氧化物层以及形成在衬底和掩埋氧化物层之间的界面层。 集成电路结构的射频区域还包括形成在掩埋氧化物层上的硅层和形成在深沟槽中的层间电介质层。 集成电路结构的射频区域还包括延伸穿过硅层，掩埋氧化物层和界面层的层间电介质层。 集成电路结构的射频区域包括形成在深沟槽中的层间电介质层下方的注入区域和形成在注入区域下方的多晶硅层。

公开(公告)号：US11264378B2

公开(公告)日：2022-03-01

申请号：US16724024

申请日：2019-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shao-Yu Chen ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Chung-Long Chang ,  Kuan-Chi Tsai ,  Wei-Kung Tsai ,  Hsiang-Chi Chen ,  Ching-Chung Hsu ,  Cheng-Chang Hsu ,  Yi-Sin Wang

IPC: H01L27/07 ,  H01L49/02 ,  H01L23/522

Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.

公开(公告)号：US10790184B2

公开(公告)日：2020-09-29

申请号：US16211949

申请日：2018-12-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Chun Lin ,  Tien-Shao Chuang ,  Kuang-Cheng Tai ,  Chun-Hung Chen ,  Chih-Hung Hsieh ,  Kuo-Hua Pan ,  Jhon-Jhy Liaw

IPC: H01L27/088 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region and a second well region that have different conductivity types and are adjacent to each other. A first fin structure protrudes from the semiconductor substrate and is formed in the first well region. A second fin structure protrudes from the semiconductor substrate and is formed in the second well region and adjacent to the first fin structure. A first multi-step isolation structure that includes a first isolation portion is formed between the first fin structure and the second fin structure. A second isolation portion extends from the bottom surface of the first isolation portion. The second isolation portion has a top width that is narrower than the bottom width of the first isolation portion.

公开(公告)号：US10515949B2

公开(公告)日：2019-12-24

申请号：US14056725

申请日：2013-10-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shao-Yu Chen ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Chung-Long Chang ,  Kuan-Chi Tsai ,  Wei-Kung Tsai ,  Hsiang-Chi Chen ,  Ching-Chung Hsu ,  Cheng-Chang Hsu ,  Yi-Sin Wang

IPC: H01L27/07 ,  H01L49/02

Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

公开(公告)号：US20150108607A1

公开(公告)日：2015-04-23

申请号：US14056725

申请日：2013-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Yu CHEN ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Chung-Long Chang ,  Kuan-Chi Tsai ,  Wei-Kung Tsai ,  Hsiang-Chi Chen ,  Ching-Chung Hsu ,  Cheng-Chang Hsu ,  Yi-Sin Wang

IPC: H01L27/07 ,  H01L23/538 ,  H01L49/02

Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract translation: 一种集成电路包括堆叠的MIM电容器和薄膜电阻器及其制造方法。 堆叠的MIM电容器的一个电容器中的电容器底部金属和薄膜电阻器基本上处于集成电路的相同层，并且电容器底部金属和薄膜电阻器也由基本上相同的材料制成。 具有层叠MIM电容器和薄膜电阻器的集成电路可以相应地以成本有益的方式制造，以克服上述缺点。

公开(公告)号：US11195760B2

公开(公告)日：2021-12-07

申请号：US16824655

申请日：2020-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hung Chen ,  Chih-Hung Hsieh ,  Jhon-Jhy Liaw

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/36 ,  H01L29/78 ,  H01L29/10 ,  H01L21/762 ,  H01L27/11 ,  H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L21/308 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/306

Abstract: A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.