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公开(公告)号：US11177810B2
公开(公告)日：2021-11-16
申请号：US17112450
申请日：2020-12-04
发明人： Feng Wei Kuo , Chewn-Pu Jou , Huan-Neng Chen , Lan-Chou Cho , Robert Bogdan Staszewski , Seyednaser Pourmousavian
摘要： An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations. The digital circuitry regulates the digital input supply voltage to stabilize the resolution of the TDC across the PVT variations. This stabilization of the resolution of the TDC can cause the ADPLL to maintain a fixed in-band phase noise across the PVT variations.
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公开(公告)号：US10971296B2
公开(公告)日：2021-04-06
申请号：US16860337
申请日：2020-04-28
发明人： Hsiao-Tsung Yen , Huan-Neng Chen , Yu-Ling Lin , Chin-Wei Kuo , Mei-Show Chen , Ho-Hsiang Chen , Min-Chie Jeng
IPC分类号： H01F27/28 , H01F17/00 , H01L23/522
摘要： A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.
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公开(公告)号：US10692963B2
公开(公告)日：2020-06-23
申请号：US15965476
申请日：2018-04-27
IPC分类号： H01F27/28 , H01L23/522 , H01L49/02 , H03L7/085 , H03L7/099
摘要： In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.
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公开(公告)号：US10326454B2
公开(公告)日：2019-06-18
申请号：US15965110
申请日：2018-04-27
发明人： Feng Wei Kuo , Chewn-Pu Jou , Huan-Neng Chen , Lan-Chou Cho , Robert Bogdan Staszewski , Seyednaser Pourmousavian
摘要： An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations. The digital circuitry regulates the digital input supply voltage to stabilize the resolution of the TDC across the PVT variations. This stabilization of the resolution of the TDC can cause the ADPLL to maintain a fixed in-band phase noise across the PVT variations.
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5.发明授权公开(公告)号：US10171089B2
公开(公告)日：2019-01-01
申请号：US15354808
申请日：2016-11-17
发明人： Feng Wei Kuo , Chewn-Pu Jou , Lan-Chou Cho , Huan-Neng Chen , Robert Bogdan Staszewski , Seyednaser Pourmousavian
摘要： An ADPLL circuit includes a time-to-digital converter (TDC) configured to generate a signal indicative of a phase difference between a first signal and a reference signal and a doubler electrically coupled to the TDC. The doubler is configured to receive a first voltage signal and generate a second voltage signal. The second voltage signal is provided to a voltage input of the TDC. The TDC is configured to generate one or more control signals for the doubler to adjust the second voltage signal.
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公开(公告)号：US09584141B2
公开(公告)日：2017-02-28
申请号：US14990583
申请日：2016-01-07
发明人： Feng-Wei Kuo , Chewn-Pu Jou , Huan-Neng Chen , Kuang-Kai Yen , Lan-Chou Cho , Robert Bogdan Staszewski , Tsung-Hsiung Lee
CPC分类号： H03L7/0991 , H03L7/00 , H03L7/0802 , H03L7/085 , H03L7/18 , H03L2207/50
摘要： A circuit and a method are disclosed herein. The circuit includes a digitally controlled oscillator and a detector. The digitally controlled oscillator is configured to generate an oscillator signal according to an oscillator tuning word. The detector is configured to output one of a first control word and a second control word that is derived from the first control word as the oscillator tuning word.
摘要翻译： 本文公开了一种电路和方法。 电路包括数字控制振荡器和检测器。 数字控制振荡器被配置为根据振荡器调谐字产生振荡器信号。 检测器被配置为输出从第一控制字导出的第一控制字和第二控制字中的一个作为振荡器调谐字。
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公开(公告)号：US08570082B1
公开(公告)日：2013-10-29
申请号：US13778478
申请日：2013-02-27
发明人： Feng Wei Kuo , Kuang-Kai Yen , Huan-Neng Chen , Hsien-Yuan Liao , Lee Tsung Hsiung , Chewn-Pu Jou , Robert Bogdan Staszewski
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , H03L1/00 , H03L7/16 , H03L2207/50
摘要： The present disclosure relates to an all digital phase locked loop (APDLL) that can account for variations in PVT conditions, and a related method of formation. In some embodiments, the ADPLL has a controllable time-to-digital converter (TDC) having a plurality of variable delay elements. The controllable TDC is determines a phase difference between a frequency reference signal and a local oscillator clock signal and to generate a phase error therefrom. A digitally controlled oscillator (DCO) varies a phase of the local oscillator clock signal based upon the phase error. A calibration unit determines an effect of variations in PVT (process, voltage, and temperature) conditions based upon the phase error and to generate a TDC tuning word that adjusts a delay introduced by one or more of the plurality of variable delay elements to account for the variations in PVT conditions.
摘要翻译： 本公开涉及可以解释PVT条件变化的全数字锁相环（APDLL）以及相关的形成方法。 在一些实施例中，ADPLL具有具有多个可变延迟元件的可控时间 - 数字转换器（TDC）。 可控TDC确定频率参考信号和本地振荡器时钟信号之间的相位差，并从其产生相位误差。 数字控制振荡器（DCO）根据相位误差改变本地振荡器时钟信号的相位。 校准单元基于相位误差来确定PVT（过程，电压和温度）变化的变化的影响，并且生成调整由多个可变延迟元件中的一个或多个引入的延迟的TDC调谐字以解释 PVT条件的变化。
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公开(公告)号：US20220326443A1
公开(公告)日：2022-10-13
申请号：US17808813
申请日：2022-06-24
发明人： Weiwei Song , Stefan Rusu , Chewn-Pu Jou , Huan-Neng Chen
摘要： A method includes etching a silicon layer to form a silicon slab and an upper silicon region over the silicon slab, and implanting the silicon slab and the upper silicon region to form a p-type region, an n-type region, and an intrinsic region between the p-type region and the n-type region. The method further includes etching the p-type region, the n-type region, and the intrinsic region to form a trench. The remaining portions of the upper silicon region form a Multi-Mode Interferometer (MMI) region. An epitaxy process is performed to grow a germanium region in the trench. Electrical connections are made to connect to the p-type region and the n-type region.
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公开(公告)号：US11257898B2
公开(公告)日：2022-02-22
申请号：US16908237
申请日：2020-06-22
IPC分类号： H01L49/02 , H01L23/522 , H01F27/28 , H03L7/085 , H03L7/099 , B01D1/00 , B01D1/12 , C02F1/04 , C02F11/12 , C02F11/18 , C02F101/30 , C02F103/14 , C02F103/16 , C02F103/28 , C02F103/32 , C02F103/34 , C02F103/36
摘要： In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.
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10.发明授权公开(公告)号：US10930603B2
公开(公告)日：2021-02-23
申请号：US15076976
申请日：2016-03-22
发明人： Feng Wei Kuo , Wen-Shiang Liao , Chewn-Pu Jou , Huan-Neng Chen , Lan-Chou Cho , William Wu Shen
IPC分类号： H01L23/66 , H01L23/552 , H01L23/498 , H01L23/00 , H01L25/18 , H01L23/522 , H01L25/065
摘要： A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground. The ground shielding layer drives radiation signals received therein to ground to prevent induced noise in the first signal path.
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