- 专利标题： PVT-free calibration function using a doubler circuit for TDC resolution in ADPLL applications
-
申请号： US15354808申请日： 2016-11-17
-
公开(公告)号： US10171089B2公开(公告)日： 2019-01-01
- 发明人: Feng Wei Kuo , Chewn-Pu Jou , Lan-Chou Cho , Huan-Neng Chen , Robert Bogdan Staszewski , Seyednaser Pourmousavian
- 申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 代理机构： Duane Morris LLP
- 主分类号： H03L7/06
- IPC分类号： H03L7/06 ; H03L1/00 ; H03L7/099 ; H03K5/151 ; H03L7/091
摘要：
An ADPLL circuit includes a time-to-digital converter (TDC) configured to generate a signal indicative of a phase difference between a first signal and a reference signal and a doubler electrically coupled to the TDC. The doubler is configured to receive a first voltage signal and generate a second voltage signal. The second voltage signal is provided to a voltage input of the TDC. The TDC is configured to generate one or more control signals for the doubler to adjust the second voltage signal.
公开/授权文献
信息查询
