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    Semiconductor devices including a thick metal layer and a bump
    2.
    发明授权
    Semiconductor devices including a thick metal layer and a bump 有权

    公开(公告)号：US11049827B2

    公开(公告)日：2021-06-29

    申请号：US16795658

    申请日：2020-02-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minjung Choi ,  Sooho Shin ,  Yeonjin Lee ,  Junghoon Han

    IPC: H01L23/00 ,  H01L21/56

    Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.

    Semiconductor devices including a thick metal layer and a bump
    4.
    发明授权
    Semiconductor devices including a thick metal layer and a bump 有权

    公开(公告)号：US11817408B2

    公开(公告)日：2023-11-14

    申请号：US18093880

    申请日：2023-01-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minjung Choi ,  Sooho Shin ,  Yeonjin Lee ,  Junghoon Han

    IPC: H01L23/00 ,  H01L21/56

    CPC classification number: H01L24/05 ,  H01L21/561 ,  H01L24/13 ,  H01L24/73 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/81801 ,  H01L2924/1304 ,  H01L2924/18162

    Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11587897B2

    公开(公告)日：2023-02-21

    申请号：US17143224

    申请日：2021-01-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joongwon Shin ,  Yeonjin Lee ,  Inyoung Lee ,  Jimin Choi ,  Jung-Hoon Han

    IPC: H01L23/29 ,  H01L23/31 ,  H01L23/00

    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a conductive pad on a first surface of the semiconductor substrate, a passivation layer on the first surface of the semiconductor substrate, the passivation layer having a first opening that exposes the conductive pad, an organic dielectric layer on the passivation layer, the organic dielectric layer having a second opening, and a bump structure on the conductive pad and in the first and second openings. The organic dielectric layer includes a material different from a material of the passivation layer. The second opening is spatially connected to the first opening and exposes a portion of the passivation layer. The bump structure includes a pillar pattern in contact with the passivation layer and the organic dielectric layer.

    Semiconductor packages
    6.
    发明授权
    Semiconductor packages 有权

    公开(公告)号：US11476220B2

    公开(公告)日：2022-10-18

    申请号：US17146550

    申请日：2021-01-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jimin Choi ,  Jung-Hoon Han ,  Yeonjin Lee ,  Jong-Min Lee ,  Jihoon Chang

    IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L21/66

    Abstract: Semiconductor packages may include a semiconductor chip on a substrate and an under-fill layer between the semiconductor chip and the substrate. The semiconductor chip may include a semiconductor substrate including first and second regions, and an interlayer dielectric layer that may cover the semiconductor substrate and may include connection lines. First conductive pads may be on the first region and may be electrically connected to some of the connection lines. Second conductive pads may be on the second region and may be electrically isolated from all of the connection lines. The semiconductor chip may also include a passivation layer that may cover the interlayer dielectric layer and may include holes that may expose the first and second conductive pads, respectively. On the second region, the under-fill layer may include a portion that may be in one of the first holes and contact one of the second conductive pads.

    SEMICONDUCTOR CHIP INCLUDING LOW-K DIELECTRIC LAYER
    7.
    发明申请
    SEMICONDUCTOR CHIP INCLUDING LOW-K DIELECTRIC LAYER 有权

    公开(公告)号：US20210057328A1

    公开(公告)日：2021-02-25

    申请号：US16848246

    申请日：2020-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yeonjin Lee ,  Junyong Noh ,  Minjung Choi ,  Junghoon Han ,  Yunrae Cho

    IPC: H01L23/522 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L23/528

    Abstract: A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

    Semiconductor devices including a thick metal layer and a bump
    8.
    发明授权
    Semiconductor devices including a thick metal layer and a bump 有权

    公开(公告)号：US12080663B2

    公开(公告)日：2024-09-03

    申请号：US18377530

    申请日：2023-10-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minjung Choi ,  Sooho Shin ,  Yeonjin Lee ,  Junghoon Han

    IPC: H01L23/00 ,  H01L21/56

    CPC classification number: H01L24/05 ,  H01L21/561 ,  H01L24/13 ,  H01L24/73 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/81801 ,  H01L2924/1304 ,  H01L2924/18162

    Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.

    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
    10.
    发明公开
    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240103070A1

    公开(公告)日：2024-03-28

    申请号：US18230373

    申请日：2023-08-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yeonjin Lee ,  Jongmin Lee

    IPC: G01R31/28 ,  H01L21/66

    CPC classification number: G01R31/2884 ,  H01L22/32

    Abstract: Provided is a semiconductor device including a substrate including an element region and a scribe lane region defining the element region, and one or more test element groups arranged on the substrate and including one or more test elements for characteristic evaluation and one or more test pads for applying a test signal for testing the one or more test elements, wherein all of the one or more test pads are spaced apart from the element region in a horizontal direction.

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