公开(公告)号：US10461030B2

公开(公告)日：2019-10-29

申请号：US15331224

申请日：2016-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Young-Ho Lee ,  Seong-Soon Cho ,  Woon-Kyung Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11582

Abstract: Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device.

公开(公告)号：US10236211B2

公开(公告)日：2019-03-19

申请号：US15956851

申请日：2018-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Jung Yun ,  Joon-Hee Lee ,  Seong-Soon Cho

IPC: H01L21/336 ,  H01L21/822 ,  H01L27/11556 ,  H01L27/11597 ,  H01L27/11578 ,  H01L27/1157 ,  H01L27/11551 ,  H01L29/792 ,  H01L29/788 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/105 ,  H01L29/78 ,  H01L27/11582 ,  H01L49/02

Abstract: A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs.

公开(公告)号：US09985041B2

公开(公告)日：2018-05-29

申请号：US15295034

申请日：2016-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Jung Yun ,  Joon-Hee Lee ,  Seong-Soon Cho

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11597 ,  H01L27/11578 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/788 ,  H01L27/105 ,  H01L29/78 ,  H01L27/11582 ,  H01L49/02

CPC classification number: H01L27/11551 ,  H01L27/1052 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11597 ,  H01L28/00 ,  H01L29/7827 ,  H01L29/7889 ,  H01L29/7926

Abstract: A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs.

公开(公告)号：US09356044B2

公开(公告)日：2016-05-31

申请号：US14975703

申请日：2015-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang-Soo Seol ,  Seong-Soon Cho

IPC: G11C11/34 ,  G11C16/04 ,  H01L27/115 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.

Abstract translation: 一种半导体器件，包括：多个存储单元串; 有位 以及将至少两个存储单元串耦合到位线的互连。 存储单元串可以通过相应的互连耦合到相应的位线。 替代的存储器单元串可以通过相应的不同互连耦合到不同的位线。