公开(公告)号：US10461030B2

公开(公告)日：2019-10-29

申请号：US15331224

申请日：2016-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Young-Ho Lee ,  Seong-Soon Cho ,  Woon-Kyung Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11582

Abstract: Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device.

公开(公告)号：US09299716B2

公开(公告)日：2016-03-29

申请号：US14790724

申请日：2015-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Won-Seok Cho

IPC: H01L29/792 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.

公开(公告)号：USRE47169E1

公开(公告)日：2018-12-18

申请号：US15047077

申请日：2016-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Yean Oh ,  Woon-Kyung Lee ,  Seung-Chul Lee

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/34

Abstract: An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.