公开(公告)号：US11729972B2

公开(公告)日：2023-08-15

申请号：US16844429

申请日：2020-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan Son ,  Seogoo Kang ,  Jeehoon Han

IPC: H10B43/27 ,  G11C8/14 ,  G11C7/18 ,  H01L29/423 ,  H01L29/792 ,  H10B43/10 ,  H01L21/28

CPC classification number: H10B43/27 ,  G11C7/18 ,  G11C8/14 ,  H01L29/4234 ,  H01L29/7926 ,  H10B43/10 ,  H01L29/40117

Abstract: A semiconductor device is disclosed. The semiconductor device includes a channel structure on a substrate and extending in a first direction perpendicular to a top surface of the substrate; a plurality of gate electrodes on the substrate and spaced apart from one another in the first direction on a sidewall of the channel structure; and a gate insulating layer between each of the plurality of gate electrodes and the channel structure, wherein the channel structure includes a body gate layer extending in the first direction; a charge storage structure surrounding a sidewall of the body gate layer; and a channel layer surrounding sidewall of the charge storage structure.

公开(公告)号：US11552098B2

公开(公告)日：2023-01-10

申请号：US16885499

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan Son ,  Sanghoon Jeong ,  Sangjun Hong ,  Seogoo Kang ,  Jeehoon Han

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: A semiconductor device includes a lower structure; a stack structure including gate layers and interlayer insulating layers and having an opening; a vertical structure in the opening; a contact structure on the vertical structure; and a conductive line on the contact structure. The vertical structure includes an insulating core region, a channel semiconductor layer covering side and lower surfaces of the insulating core region, data storage patterns between the channel semiconductor layer and the gate layers and spaced apart from each other, a first dielectric layer, and a second dielectric layer. At least a portion of the first dielectric layer is between the data storage patterns and the gate layers, at least a portion of the second dielectric layer is between the data storage patterns and the channel semiconductor layer, and the insulating core region includes first convex portions having increased widths in regions facing the gate layers.

公开(公告)号：US20230157023A1

公开(公告)日：2023-05-18

申请号：US18094007

申请日：2023-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan Son ,  Sanghoon Jeong ,  Sangjun Hong ,  Seogoo Kang ,  Jeehoon Han

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor device includes a lower structure; a stack structure including gate layers and interlayer insulating layers and having an opening; a vertical structure in the opening; a contact structure on the vertical structure; and a conductive line on the contact structure. The vertical structure includes an insulating core region, a channel semiconductor layer covering side and lower surfaces of the insulating core region, data storage patterns between the channel semiconductor layer and the gate layers and spaced apart from each other, a first dielectric layer, and a second dielectric layer. At least a portion of the first dielectric layer is between the data storage patterns and the gate layers, at least a portion of the second dielectric layer is between the data storage patterns and the channel semiconductor layer, and the insulating core region includes first convex portions having increased widths in regions facing the gate layers.

公开(公告)号：US11594544B2

公开(公告)日：2023-02-28

申请号：US16942456

申请日：2020-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojoon Ryu ,  Younghwan Son ,  Seogoo Kang ,  Jesuk Moon ,  Junghoon Jun ,  Kohji Kanamori ,  Jeehoon Han

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565

Abstract: A semiconductor device includes; gate layers stacked on a substrate, a channel layer extending through the gate layers, a string select gate layer disposed on the channel layer and a string select channel layer extending through the string select gate layer to contact the channel layer. The string select channel layer includes a first portion below the string select gate layer including a first protruding region, a second portion extending through the string select gate layer, and a third portion above the string select gate layer including a second protruding region.

公开(公告)号：US11716851B2

公开(公告)日：2023-08-01

申请号：US17400224

申请日：2021-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji Kanamori ,  Seogoo Kang ,  Shinhwan Kang

IPC: H10B43/27 ,  H01L29/417

CPC classification number: H10B43/27 ,  H01L29/41741

Abstract: A semiconductor memory device including a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer between the first and second semiconductor layers, gate electrodes arranged on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer, and channel structures penetrating the first, second and third semiconductor layers and the gate electrodes, each respective channel structure of channel structures including a gate insulating film, a channel layer, and a buried insulating film, the gate insulating film including a tunnel insulating film adjacent to the channel layer, a charge blocking film adjacent to the gate electrodes, and a charge storage film between the tunnel insulating film and the charge blocking film, and the charge storage film including an upper cover protruding toward the outside of the respective channel structure.

公开(公告)号：US11515322B2

公开(公告)日：2022-11-29

申请号：US16890500

申请日：2020-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seogoo Kang ,  Daehyun Jang ,  Jaeryong Sim ,  Jongseon Ahn ,  Jeehoon Han

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/11548 ,  H01L27/11556

Abstract: A semiconductor device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate; and a memory cell region including a second substrate on an upper portion of the first substrate, gate electrodes spaced apart from each other and vertically stacked on the second substrate, channel structures extending vertically through the gate electrodes to the second substrate, first separation regions penetrating through the gate electrodes between the channel structures and extending in one direction, and a second separation region extending vertically to penetrate through the second substrate from above and having a bent portion due to a change in width.

公开(公告)号：US20240324221A1

公开(公告)日：2024-09-26

申请号：US18612110

申请日：2024-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Seogoo Kang ,  Kyungdong Kim ,  Seunghyun Lee ,  Jeehoon Han

IPC: H10B43/27 ,  G11C5/06 ,  G11C16/04 ,  G11C16/08 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06506

Abstract: A memory device is provided. The memory device includes a first cell array stack including first gate electrodes, a first channel structure, and first pad portions respectively connected to the first gate electrodes and having a step shape, a second cell array stack disposed on the first cell array stack and including second gate electrodes, a second channel structure, and second pad portions respectively connected to the second gate electrodes and having a step shape, wherein the second pad portions overlap the first pad portions in the first direction, and a vertical contact passing through any one of the first pad portions, first extension portions below the any one of the first pad portions, any one of the second pad portions, and second extension portions below the any one of the second pad portions, to extend in the first direction.

公开(公告)号：US11374017B2

公开(公告)日：2022-06-28

申请号：US16842055

申请日：2020-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Seogoo Kang ,  Jongseon Ahn ,  Jeehoon Han

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11519 ,  H01L27/11582

Abstract: A three-dimensional memory device is provided. The three-dimensional memory device may include a substrate, a cell stack, a string selection line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string selection line gate electrode may include a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode. The lower string selection line gate electrode may include N-doped poly-crystalline silicon. The upper string selection line gate electrode may include silicide.

公开(公告)号：US11114460B2

公开(公告)日：2021-09-07

申请号：US16690929

申请日：2019-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji Kanamori ,  Seogoo Kang ,  Shinhwan Kang

IPC: H01L27/11582 ,  H01L29/417

Abstract: A semiconductor memory device including a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer between the first and second semiconductor layers, gate electrodes arranged on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer, and channel structures penetrating the first, second and third semiconductor layers and the gate electrodes, each respective channel structure of channel structures including a gate insulating film, a channel layer, and a buried insulating film, the gate insulating film including a tunnel insulating film adjacent to the channel layer, a charge blocking film adjacent to the gate electrodes, and a charge storage film between the tunnel insulating film and the charge blocking film, and the charge storage film including an upper cover protruding toward the outside of the respective channel structure.

公开(公告)号：US20210091093A1

公开(公告)日：2021-03-25

申请号：US16842055

申请日：2020-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Seogoo Kang ,  Jongseon Ahn ,  Jeehoon Han

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11519 ,  H01L27/11565

Abstract: A three-dimensional memory device is provided. The three-dimensional memory device may include a substrate, a cell stack, a string selection line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string selection line gate electrode may include a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode. The lower string selection line gate electrode may include N-doped poly-crystalline silicon. The upper string selection line gate electrode may include silicide.