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    Semiconductor device and manufacturing method of the same
    1.
    发明授权
    Semiconductor device and manufacturing method of the same 有权

    公开(公告)号：US11557604B2

    公开(公告)日：2023-01-17

    申请号：US17025120

    申请日：2020-09-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seongyeon Woo ,  Sangjun Hong ,  Jinsoo Lim ,  Jisung Cheon

    IPC: H01L27/11582 ,  H01L27/11565 ,  G11C8/14 ,  H01L27/11556 ,  H01L27/11519

    Abstract: A semiconductor device includes: a first gate stack including a plurality of first gate electrodes; a second gate stack arranged on the first gate stack and including a plurality of second gate electrodes; and a plurality of channel structures arranged in a plurality of channel holes penetrating the first gate stack and the second gate stack. Each of the channel holes includes a first channel hole portion penetrating the first gate stack and a second channel hole portion penetrating the second gate stack, and a ratio of a second width in the second direction to a first width in the first direction of an upper end of the first channel hole portion is less than a ratio of a fourth width in the second direction to a third width in the first direction of an upper end of the second channel hole portion.

    SEMICONDUCTOR DEVICE HAVING WORD LINE SEPARATION LAYER
    2.
    发明申请
    SEMICONDUCTOR DEVICE HAVING WORD LINE SEPARATION LAYER 有权

    公开(公告)号：US20230032392A1

    公开(公告)日：2023-02-02

    申请号：US17934959

    申请日：2022-09-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jiye Noh ,  Jinsoo Lim ,  Daehyun Jang ,  Jisung Cheon ,  Sangjun Hong

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/528 ,  H01L23/48

    Abstract: A semiconductor device includes a peripheral circuit structure; a lower stack disposed on the peripheral circuit structure and an upper stack disposed in the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array area; a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a horizontal direction, the pair of separation insulating layers being spaced apart from each other in a vertical direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer extending vertically through at least one of the lower word lines.

    Semiconductor device having word line separation layer
    3.
    发明授权
    Semiconductor device having word line separation layer 有权

    公开(公告)号：US11456316B2

    公开(公告)日：2022-09-27

    申请号：US16926045

    申请日：2020-07-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jiye Noh ,  Jinsoo Lim ,  Daehyun Jang ,  Jisung Cheon ,  Sangjun Hong

    IPC: H01L27/11582 ,  H01L23/48 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565

    Abstract: A semiconductor device includes a peripheral circuit structure disposed on a substrate; a lower stack disposed on the peripheral circuit structure and an upper stack disposed in the lower stack, the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array area; a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a horizontal direction, the pair of separation insulating layers being spaced apart from each other in a vertical direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer extending vertically through at least one of the lower word lines.

    SEMICONDUCTOR DEVICE INCLUDING DATA STORAGE PATTERN
    5.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING DATA STORAGE PATTERN 有权

    公开(公告)号：US20210074720A1

    公开(公告)日：2021-03-11

    申请号：US16885499

    申请日：2020-05-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Younghwan Son ,  Sanghoon Jeong ,  Sangjun Hong ,  Seogoo Kang ,  Jeehoon Han

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

    Abstract: A semiconductor device includes a lower structure; a stack structure including gate layers and interlayer insulating layers and having an opening; a vertical structure in the opening; a contact structure on the vertical structure; and a conductive line on the contact structure. The vertical structure includes an insulating core region, a channel semiconductor layer covering side and lower surfaces of the insulating core region, data storage patterns between the channel semiconductor layer and the gate layers and spaced apart from each other, a first dielectric layer, and a second dielectric layer. At least a portion of the first dielectric layer is between the data storage patterns and the gate layers, at least a portion of the second dielectric layer is between the data storage patterns and the channel semiconductor layer, and the insulating core region includes first convex portions having increased widths in regions facing the gate layers.

    Integrated circuit device
    6.
    发明授权
    Integrated circuit device 有权

    公开(公告)号：US12219763B2

    公开(公告)日：2025-02-04

    申请号：US17744092

    申请日：2022-05-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jisung Cheon ,  Byunggon Park ,  Joowon Park ,  Sangjun Hong ,  Jinsoo Lim

    IPC: H10B43/27 ,  H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

    Abstract: An integrated circuit device including a substrate having a cell and interconnection region; and a first stacked structure and a second stacked structure on the first stacked structure, each of the first and second stacked structures including insulating layers and word line structures that are alternately stacked one by one on the substrate in the cell region and the interconnection region, wherein, in the interconnection region the first stacked structure includes a first dummy channel hole penetrating through the first stacked structure, the second stacked structure includes a second dummy channel hole communicatively connected to the first dummy channel hole, the second dummy channel hole penetrating through the second stacked structure, respectively, and a first dummy upper width of an uppermost end of the first dummy channel hole is greater than a second dummy upper width of an uppermost end of the second dummy channel hole.

    Semiconductor memory device and method of manufacturing the same
    7.
    发明授权
    Semiconductor memory device and method of manufacturing the same 有权

    公开(公告)号：US11653493B2

    公开(公告)日：2023-05-16

    申请号：US16874159

    申请日：2020-05-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sanghoon Jeong ,  Sangjun Hong ,  Sunil Shim ,  Kyunghyun Kim ,  Changsup Mun

    IPC: H01L27/11568 ,  H01L27/11556 ,  G11C5/02 ,  H01L27/11582

    CPC classification number: H01L27/11556 ,  G11C5/025 ,  H01L27/11582

    Abstract: A semiconductor memory device includes a stack structure comprising horizontal electrodes sequentially stacked on a substrate including a cell array region and an extension region and horizontal insulating layers between the horizontal electrodes. The semiconductor memory device may further include vertical structures that penetrate the stack structure, a first one of the vertical structures being on the cell array region and a second one of the vertical structures being on the extension region. Each of the vertical structures includes a channel layer, and a tunneling insulating layer, a charge storage layer and a blocking insulating layer which are sequentially stacked on a sidewall of the channel layer. The charge storage layer of the first vertical structure includes charge storage patterns spaced apart from each other in a direction perpendicular to a top surface of the substrate with the horizontal insulating layers interposed therebetween. The charge storage layer of the second vertical structure extends along sidewalls of the horizontal electrodes and sidewalls of the horizontal insulating layers.

    Semiconductor device including data storage pattern with improved retention characteristics
    8.
    发明授权
    Semiconductor device including data storage pattern with improved retention characteristics 有权

    公开(公告)号：US11552098B2

    公开(公告)日：2023-01-10

    申请号：US16885499

    申请日：2020-05-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Younghwan Son ,  Sanghoon Jeong ,  Sangjun Hong ,  Seogoo Kang ,  Jeehoon Han

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

    Abstract: A semiconductor device includes a lower structure; a stack structure including gate layers and interlayer insulating layers and having an opening; a vertical structure in the opening; a contact structure on the vertical structure; and a conductive line on the contact structure. The vertical structure includes an insulating core region, a channel semiconductor layer covering side and lower surfaces of the insulating core region, data storage patterns between the channel semiconductor layer and the gate layers and spaced apart from each other, a first dielectric layer, and a second dielectric layer. At least a portion of the first dielectric layer is between the data storage patterns and the gate layers, at least a portion of the second dielectric layer is between the data storage patterns and the channel semiconductor layer, and the insulating core region includes first convex portions having increased widths in regions facing the gate layers.

    SEMICONDUCTOR DEVICE INCLUDING DATA STORAGE PATTERN
    10.
    发明公开
    SEMICONDUCTOR DEVICE INCLUDING DATA STORAGE PATTERN 审中-公开

    公开(公告)号：US20230157023A1

    公开(公告)日：2023-05-18

    申请号：US18094007

    申请日：2023-01-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Younghwan Son ,  Sanghoon Jeong ,  Sangjun Hong ,  Seogoo Kang ,  Jeehoon Han

    IPC: H10B43/27 ,  H10B43/10 ,  H10B43/35

    CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/35

    Abstract: A semiconductor device includes a lower structure; a stack structure including gate layers and interlayer insulating layers and having an opening; a vertical structure in the opening; a contact structure on the vertical structure; and a conductive line on the contact structure. The vertical structure includes an insulating core region, a channel semiconductor layer covering side and lower surfaces of the insulating core region, data storage patterns between the channel semiconductor layer and the gate layers and spaced apart from each other, a first dielectric layer, and a second dielectric layer. At least a portion of the first dielectric layer is between the data storage patterns and the gate layers, at least a portion of the second dielectric layer is between the data storage patterns and the channel semiconductor layer, and the insulating core region includes first convex portions having increased widths in regions facing the gate layers.

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