公开(公告)号：US11233068B2

公开(公告)日：2022-01-25

申请号：US17193187

申请日：2021-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-soon Lim ,  Jin-young Kim ,  Sang-won Shim ,  Il-han Park

IPC: G11C11/34 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/535 ,  G11C16/04 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11575 ,  H01L27/1157

Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.

公开(公告)号：US20200065029A1

公开(公告)日：2020-02-27

申请号：US16394506

申请日：2019-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyun Kim ,  Chankyung Kim ,  Sang-won Shim ,  Suk-Soo Pyo

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

Abstract: An operating method of a storage device which includes a first nonvolatile memory device and a second nonvolatile memory device includes detecting sudden power-off, suspending an operation being performed in the first nonvolatile memory device, in response to the detected sudden power-off, writing suspension information about the suspended operation into the second nonvolatile memory device, and performing a block management operation on the first nonvolatile memory device based on the suspension information written into the second nonvolatile memory device, in power-up after the sudden power-off.

公开(公告)号：US20200312379A1

公开(公告)日：2020-10-01

申请号：US16591061

申请日：2019-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongsoon Lim ,  Hojoon Kim ,  Sang-won Park ,  Sang-won Shim ,  Wonbo Shim

IPC: G11C5/02 ,  G11C8/08 ,  G11C8/06 ,  G11C8/18 ,  G11C5/06 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor memory device includes a substrate, first memory cells that are connected to first word lines extending along a first direction and first bit lines extending along a second direction, over the substrate, first conductive materials that are connected to the first word lines and extend from the first word lines along a third direction perpendicular to the first direction and the second direction, second conductive materials that are connected to the first bit lines and extend along the first direction over the first bit lines, and third conductive materials that are connected to the second conductive materials and extend from the second conductive materials along the third direction.

公开(公告)号：US10672791B2

公开(公告)日：2020-06-02

申请号：US16200714

申请日：2018-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-soon Lim ,  Jin-young Kim ,  Sang-won Shim ,  Il-han Park

IPC: G11C11/34 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/535 ,  G11C16/04 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11575 ,  H01L27/1157

Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.

公开(公告)号：US11112997B2

公开(公告)日：2021-09-07

申请号：US16394506

申请日：2019-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyun Kim ,  Chankyung Kim ,  Sang-won Shim ,  Suk-Soo Pyo

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

Abstract: An operating method of a storage device which includes a first nonvolatile memory device and a second nonvolatile memory device includes detecting sudden power-off, suspending an operation being performed in the first nonvolatile memory device, in response to the detected sudden power-off, writing suspension information about the suspended operation into the second nonvolatile memory device, and performing a block management operation on the first nonvolatile memory device based on the suspension information written into the second nonvolatile memory device, in power-up after the sudden power-off.

公开(公告)号：US11011208B2

公开(公告)日：2021-05-18

申请号：US16591061

申请日：2019-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongsoon Lim ,  Hojoon Kim ,  Sang-won Park ,  Sang-won Shim ,  Wonbo Shim

IPC: G11C5/02 ,  G11C8/08 ,  G11C8/06 ,  G11C8/14 ,  G11C5/06 ,  G11C7/18 ,  G11C8/18

Abstract: A semiconductor memory device includes a substrate, first memory cells that are connected to first word lines extending along a first direction and first bit lines extending along a second direction, over the substrate, first conductive materials that are connected to the first word lines and extend from the first word lines along a third direction perpendicular to the first direction and the second direction, second conductive materials that are connected to the first bit lines and extend along the first direction over the first bit lines, and third conductive materials that are connected to the second conductive materials and extend from the second conductive materials along the third direction.

公开(公告)号：US20170373084A1

公开(公告)日：2017-12-28

申请号：US15429474

申请日：2017-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-won Shim ,  Bong-soon LIM

IPC: H01L27/11573 ,  H01L27/11565 ,  H01L23/528 ,  H01L27/11582 ,  H01L23/522

CPC classification number: H01L27/11573 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11582

Abstract: A memory device includes a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and upper bit lines. The first semiconductor layer includes lower bit lines that extend in a first direction and are parallel to each other in a second direction perpendicular to the first direction, and a substrate. The second semiconductor layer includes vertical pillars extending in a third direction that is perpendicular to the first and second directions. The upper bit lines are connected to the vertical pillars and extend in the first direction on the second semiconductor layer. The upper bit lines are arranged to have a first pitch in the second direction. The lower bit lines are arranged to have a second pitch in the second direction. The first pitch and the second pitch have different lengths.

公开(公告)号：US11532634B2

公开(公告)日：2022-12-20

申请号：US16035995

申请日：2018-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-won Shim ,  Bong-soon Lim

IPC: H01L27/115 ,  G11C16/24 ,  G11C7/10 ,  G11C5/14 ,  G11C16/30 ,  G11C5/02 ,  H01L27/11526 ,  G11C16/08 ,  G11C16/04 ,  G11C7/18 ,  G11C8/14

Abstract: A nonvolatile memory device comprises a first semiconductor layer including, an upper substrate, and a memory cell array in which a plurality of word lines on the upper substrate extend in a first direction and a plurality of bit lines extend in a second direction. The nonvolatile memory device comprises a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer including, a lower substrate, and a substrate control circuit on the lower substrate and configured to output a bias voltage to the upper substrate. The second semiconductor layer is divided into first through fourth regions, each of the first through fourth regions having an identical area, and the substrate control circuit overlaps at least a portion of the first through fourth regions in the third direction.

公开(公告)号：US11211403B2

公开(公告)日：2021-12-28

申请号：US17073653

申请日：2020-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-soon Lim ,  Jin-young Kim ,  Sang-won Shim ,  Il-han Park

IPC: G11C11/34 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/535 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11575 ,  G11C16/04

Abstract: A nonvolatile memory device including: a first semiconductor layer comprising a plurality of first word lines extending in a first direction, a first upper substrate and a first memory cell array, a second semiconductor layer including a plurality of second word lines extending in the first direction, second and third upper substrates adjacent to each other in the first direction and a second memory cell array, wherein the second memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, wherein the first semiconductor layer and the second semiconductor layer share a plurality of bit lines extending in a second direction, and a third semiconductor layer under the second semiconductor layer in a third direction perpendicular to the first and second directions, wherein the third semiconductor layer includes a lower substrate that includes a plurality of row decoder circuits and a plurality of page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area in the first direction.

公开(公告)号：US10978481B2

公开(公告)日：2021-04-13

申请号：US16861939

申请日：2020-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-soon Lim ,  Jin-young Kim ,  Sang-won Shim ,  Il-han Park

IPC: G11C11/34 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/535 ,  G11C16/04 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11575 ,  H01L27/1157

Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.