公开(公告)号：US11233068B2

公开(公告)日：2022-01-25

申请号：US17193187

申请日：2021-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-soon Lim ,  Jin-young Kim ,  Sang-won Shim ,  Il-han Park

IPC: G11C11/34 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/535 ,  G11C16/04 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11575 ,  H01L27/1157

Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.

公开(公告)号：US10672791B2

公开(公告)日：2020-06-02

申请号：US16200714

申请日：2018-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-soon Lim ,  Jin-young Kim ,  Sang-won Shim ,  Il-han Park

IPC: G11C11/34 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/535 ,  G11C16/04 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11575 ,  H01L27/1157

Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.

公开(公告)号：US10700079B2

公开(公告)日：2020-06-30

申请号：US16193007

申请日：2018-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： June-hong Park ,  Bong-soon Lim ,  Il-han Park

IPC: H01L27/11556 ,  H01L27/06 ,  H01L23/535 ,  H01L21/8234 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11531 ,  H01L27/11573 ,  H01L27/112

Abstract: A nonvolatile memory device and a method of manufacturing the device, the device including a first semiconductor layer, the first semiconductor layer including an upper substrate, and a memory cell array, the memory cell array including a plurality of gate conductive layers stacked on the upper substrate and a plurality of pillars passing through the plurality of gate conductive layers and extending in a direction perpendicular to a top surface of the upper substrate; and a second semiconductor layer under the first semiconductor layer, the second semiconductor layer including a lower substrate, at least one contact plug between the lower substrate and the upper substrate, and a common source line driver on the lower substrate and configured to output a common source voltage for the plurality of pillars through the at least one contact plug.

公开(公告)号：US11532634B2

公开(公告)日：2022-12-20

申请号：US16035995

申请日：2018-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-won Shim ,  Bong-soon Lim

IPC: H01L27/115 ,  G11C16/24 ,  G11C7/10 ,  G11C5/14 ,  G11C16/30 ,  G11C5/02 ,  H01L27/11526 ,  G11C16/08 ,  G11C16/04 ,  G11C7/18 ,  G11C8/14

Abstract: A nonvolatile memory device comprises a first semiconductor layer including, an upper substrate, and a memory cell array in which a plurality of word lines on the upper substrate extend in a first direction and a plurality of bit lines extend in a second direction. The nonvolatile memory device comprises a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer including, a lower substrate, and a substrate control circuit on the lower substrate and configured to output a bias voltage to the upper substrate. The second semiconductor layer is divided into first through fourth regions, each of the first through fourth regions having an identical area, and the substrate control circuit overlaps at least a portion of the first through fourth regions in the third direction.

公开(公告)号：US11211403B2

公开(公告)日：2021-12-28

申请号：US17073653

申请日：2020-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-soon Lim ,  Jin-young Kim ,  Sang-won Shim ,  Il-han Park

IPC: G11C11/34 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/535 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11575 ,  G11C16/04

Abstract: A nonvolatile memory device including: a first semiconductor layer comprising a plurality of first word lines extending in a first direction, a first upper substrate and a first memory cell array, a second semiconductor layer including a plurality of second word lines extending in the first direction, second and third upper substrates adjacent to each other in the first direction and a second memory cell array, wherein the second memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, wherein the first semiconductor layer and the second semiconductor layer share a plurality of bit lines extending in a second direction, and a third semiconductor layer under the second semiconductor layer in a third direction perpendicular to the first and second directions, wherein the third semiconductor layer includes a lower substrate that includes a plurality of row decoder circuits and a plurality of page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area in the first direction.

公开(公告)号：US10978481B2

公开(公告)日：2021-04-13

申请号：US16861939

申请日：2020-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-soon Lim ,  Jin-young Kim ,  Sang-won Shim ,  Il-han Park

IPC: G11C11/34 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/535 ,  G11C16/04 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11575 ,  H01L27/1157

Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.