公开(公告)号：US20190035788A1

公开(公告)日：2019-01-31

申请号：US16152832

申请日：2018-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： MUN-HYEON KIM ,  SOO-HYEON KIM ,  BYOUNG-HAK HONG ,  KEUN-HWI CHO ,  TOSHINORI FUKAI ,  SHIGENOBU MAEDA ,  HIDENOBU FUKUTOME

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a gate structure, a first impurity region, and a second impurity region. The gate structure may cross over a first active region and a second active region of the substrate. The first insulation structure including a first insulation material may be formed on the first active region, and may be spaced apart from opposite sides of the gate structure. The second insulation structure including a second insulation material different from the first insulation material may be formed on the second active region, and may be spaced apart from opposite sides of the gate structure. The first impurity region may be formed at a portion of the first active region between the gate structure and the first insulation structure, and may be doped with p-type impurities. The second impurity region may be formed at a portion of the second active region between the gate structure and the second insulation structure, and may be doped with n-type, impurities. A stress may be applied onto a channel region of a transistor, so that the semiconductor device may have good electrical characteristics.

公开(公告)号：US20230023762A1

公开(公告)日：2023-01-26

申请号：US17719722

申请日：2022-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIHO KIM ,  MINHYEOK KWON ,  SHIGENOBU MAEDA ,  JOOYEOK SEO ,  MINUK LEE

IPC: H01L21/67 ,  G05B19/418

Abstract: The program code, when executed by a processor, causes the processor to input fabrication data including a plurality of parameters associated with a semiconductor fabricating process to a framework to generate a first class for analyzing the fabrication data, to extract a first parameter targeted for analysis and a second parameter associated with the first parameter from the plurality of parameters and generate a second class for analyzing the first parameter as a sub class of the first class, to modify the first parameter and the second parameter into a data structure having a format appropriate to store in the second class, so as to be stored in the second class, to perform data analysis on the first parameter and the second parameter, to transform the first parameter and the second parameter into corresponding tensor data, and to input the tensor data to the machine learning model.

公开(公告)号：US20230127871A1

公开(公告)日：2023-04-27

申请号：US17877251

申请日：2022-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHOONGSUN KIM ,  SHIGENOBU MAEDA ,  MYOUNGKYU PARK

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238

Abstract: A method of manufacturing a semiconductor device includes forming an active fin protruding from a substrate and extending in a first direction; forming sacrificial gate patterns intersecting the active fin and extend in a second direction; forming recess regions by etching the active fin on at least one side of each of the sacrificial gate patterns; forming source/drain regions on the recess regions; removing the sacrificial gate patterns to form openings; and forming a gate dielectric layer and a gate electrode such that gate structures are formed to cover the active fin in the openings. The source/drain regions are formed by an epitaxial growth process and an in-situ doping process of doping first conductivity-type impurity elements. In at least one of the source/drain regions, after the in-situ doping process is performed, counter-doping is performed using second conductivity-type impurity elements different from the first conductivity-type impurity elements to decrease carrier concentration.

公开(公告)号：US20170162574A1

公开(公告)日：2017-06-08

申请号：US15209328

申请日：2016-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MUN-HYEON KIM ,  SOO-HYEON KIM ,  BYOUNG-HAK HONG ,  KEUN-HWI CHO ,  TOSHINORI FUKAI ,  SHIGENOBU MAEDA ,  HIDENOBU FUKUTOME

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, a gate structure, a first impurity region, and a second impurity region. The gate structure may cross over a first active region and a second active region of the substrate. The first insulation structure including a first insulation material may be formed on the first active region, and may be spaced apart from opposite sides of the gate structure. The second insulation structure including a second insulation material different from the first insulation material may be formed on the second active region, and may be spaced apart from opposite sides of the gate structure. The first impurity region may be formed at a portion of the first active region between the gate structure and the first insulation structure, and may be doped with p-type impurities. The second impurity region may be formed at a portion of the second active region between the gate structure and the second insulation structure, and may be doped with n-type impurities. A stress may be applied onto a channel region of a transistor, so that the semiconductor device may have good electrical characteristics.

公开(公告)号：US20180308705A1

公开(公告)日：2018-10-25

申请号：US16023836

申请日：2018-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： SHIGENOBU MAEDA ,  Jeong Ju PARK ,  Eunsung KIM ,  Hyunwoo KIM ,  Shiyong YI

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method includes forming mask patterns spaced apart from each other by at least one opening on an etch target layer, filling the opening with a block copolymer material including first and second polymer blocks of different properties, and annealing the block copolymer material to form first patterns and second patterns, the first patterns in contact with facing sidewalls of adjacent ones of the mask patterns, respectively, and at least one of the second patterns between the first patterns. The first patterns include the first polymer blocks and the second patterns include the second polymer blocks.

公开(公告)号：US20170103986A1

公开(公告)日：2017-04-13

申请号：US15231134

申请日：2016-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MUN-HYEON KIM ,  CHANG-WOO NOH ,  KEUN-HWI CHO ,  MYUNG-GIL KANG ,  SHIGENOBU MAEDA

IPC: H01L27/092

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51

Abstract: Disclosed are CMOS device and CMOS inverter. The CMOS device includes a substrate having active lines extending in a first direction and defined by a device isolation layer, the substrate being divided into an NMOS area, a PMOS area and a boundary area interposed between the NMOPS and the PMOS areas and having the device isolation layer without the active line, a gate line extending in a second direction across the active lines and having a first gate structure on the active line in the first area, a second gate structure on the active line in the second and a third gate structure on the device isolation layer in the third area. The electrical resistance and parasitic capacitance of the third gate structure are smaller than those of the NMOS and the PMOS gate structures. Accordingly, better AC and DC performance of the CMOS device can be obtained.