公开(公告)号：US20170162574A1

公开(公告)日：2017-06-08

申请号：US15209328

申请日：2016-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MUN-HYEON KIM ,  SOO-HYEON KIM ,  BYOUNG-HAK HONG ,  KEUN-HWI CHO ,  TOSHINORI FUKAI ,  SHIGENOBU MAEDA ,  HIDENOBU FUKUTOME

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, a gate structure, a first impurity region, and a second impurity region. The gate structure may cross over a first active region and a second active region of the substrate. The first insulation structure including a first insulation material may be formed on the first active region, and may be spaced apart from opposite sides of the gate structure. The second insulation structure including a second insulation material different from the first insulation material may be formed on the second active region, and may be spaced apart from opposite sides of the gate structure. The first impurity region may be formed at a portion of the first active region between the gate structure and the first insulation structure, and may be doped with p-type impurities. The second impurity region may be formed at a portion of the second active region between the gate structure and the second insulation structure, and may be doped with n-type impurities. A stress may be applied onto a channel region of a transistor, so that the semiconductor device may have good electrical characteristics.

公开(公告)号：US20190035788A1

公开(公告)日：2019-01-31

申请号：US16152832

申请日：2018-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： MUN-HYEON KIM ,  SOO-HYEON KIM ,  BYOUNG-HAK HONG ,  KEUN-HWI CHO ,  TOSHINORI FUKAI ,  SHIGENOBU MAEDA ,  HIDENOBU FUKUTOME

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a gate structure, a first impurity region, and a second impurity region. The gate structure may cross over a first active region and a second active region of the substrate. The first insulation structure including a first insulation material may be formed on the first active region, and may be spaced apart from opposite sides of the gate structure. The second insulation structure including a second insulation material different from the first insulation material may be formed on the second active region, and may be spaced apart from opposite sides of the gate structure. The first impurity region may be formed at a portion of the first active region between the gate structure and the first insulation structure, and may be doped with p-type impurities. The second impurity region may be formed at a portion of the second active region between the gate structure and the second insulation structure, and may be doped with n-type, impurities. A stress may be applied onto a channel region of a transistor, so that the semiconductor device may have good electrical characteristics.