公开(公告)号：US20170162574A1

公开(公告)日：2017-06-08

申请号：US15209328

申请日：2016-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MUN-HYEON KIM ,  SOO-HYEON KIM ,  BYOUNG-HAK HONG ,  KEUN-HWI CHO ,  TOSHINORI FUKAI ,  SHIGENOBU MAEDA ,  HIDENOBU FUKUTOME

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, a gate structure, a first impurity region, and a second impurity region. The gate structure may cross over a first active region and a second active region of the substrate. The first insulation structure including a first insulation material may be formed on the first active region, and may be spaced apart from opposite sides of the gate structure. The second insulation structure including a second insulation material different from the first insulation material may be formed on the second active region, and may be spaced apart from opposite sides of the gate structure. The first impurity region may be formed at a portion of the first active region between the gate structure and the first insulation structure, and may be doped with p-type impurities. The second impurity region may be formed at a portion of the second active region between the gate structure and the second insulation structure, and may be doped with n-type impurities. A stress may be applied onto a channel region of a transistor, so that the semiconductor device may have good electrical characteristics.

公开(公告)号：US20190035788A1

公开(公告)日：2019-01-31

申请号：US16152832

申请日：2018-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： MUN-HYEON KIM ,  SOO-HYEON KIM ,  BYOUNG-HAK HONG ,  KEUN-HWI CHO ,  TOSHINORI FUKAI ,  SHIGENOBU MAEDA ,  HIDENOBU FUKUTOME

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a gate structure, a first impurity region, and a second impurity region. The gate structure may cross over a first active region and a second active region of the substrate. The first insulation structure including a first insulation material may be formed on the first active region, and may be spaced apart from opposite sides of the gate structure. The second insulation structure including a second insulation material different from the first insulation material may be formed on the second active region, and may be spaced apart from opposite sides of the gate structure. The first impurity region may be formed at a portion of the first active region between the gate structure and the first insulation structure, and may be doped with p-type impurities. The second impurity region may be formed at a portion of the second active region between the gate structure and the second insulation structure, and may be doped with n-type, impurities. A stress may be applied onto a channel region of a transistor, so that the semiconductor device may have good electrical characteristics.

公开(公告)号：US20170103986A1

公开(公告)日：2017-04-13

申请号：US15231134

申请日：2016-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MUN-HYEON KIM ,  CHANG-WOO NOH ,  KEUN-HWI CHO ,  MYUNG-GIL KANG ,  SHIGENOBU MAEDA

IPC: H01L27/092

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51

Abstract: Disclosed are CMOS device and CMOS inverter. The CMOS device includes a substrate having active lines extending in a first direction and defined by a device isolation layer, the substrate being divided into an NMOS area, a PMOS area and a boundary area interposed between the NMOPS and the PMOS areas and having the device isolation layer without the active line, a gate line extending in a second direction across the active lines and having a first gate structure on the active line in the first area, a second gate structure on the active line in the second and a third gate structure on the device isolation layer in the third area. The electrical resistance and parasitic capacitance of the third gate structure are smaller than those of the NMOS and the PMOS gate structures. Accordingly, better AC and DC performance of the CMOS device can be obtained.

公开(公告)号：US20170033217A1

公开(公告)日：2017-02-02

申请号：US15094282

申请日：2016-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BYOUNG-HAK HONG ,  BON-WOONG KOO ,  SUNG-IL PARK ,  KYU-BAIK CHANG ,  KEUN-HWI CHO ,  DAE-WON HA

IPC: H01L29/78 ,  H01L29/423 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L27/0924 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a gate structure on a substrate. The gate structure includes a first gate insulation pattern, a conductive pattern for controlling a threshold voltage, a first gate electrode and a first mask sequentially stacked. A dummy gate structure is spaced apart from the gate electrode. The dummy gate structure includes a first stressor pattern including titanium oxide. Source/drain regions are adjacent to the gate structure. The source/drain regions are doped with p-type impurities. The first stressor pattern may apply a stress onto the channel region of a transistor, and consequently the transistor having good electrical characteristics may be obtained.

Abstract translation: 半导体器件包括在衬底上的栅极结构。 栅极结构包括第一栅极绝缘图案，用于控制阈值电压的导电图案，第一栅电极和顺序层叠的第一掩模。 虚栅极结构与栅电极间隔开。 虚拟栅极结构包括包括氧化钛的第一应力源图案。 源极/漏极区域与栅极结构相邻。 源/漏区掺杂有p型杂质。 第一应力源图案可以在晶体管的沟道区域施加应力，因此可以获得具有良好电特性的晶体管。