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    SEMICONDUCTOR DEVICE INCLUDING VERTICAL ACTIVE PILLAR
    1.
    发明公开
    SEMICONDUCTOR DEVICE INCLUDING VERTICAL ACTIVE PILLAR 审中-公开

    公开(公告)号：US20240276712A1

    公开(公告)日：2024-08-15

    申请号：US18435263

    申请日：2024-02-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hongjun LEE ,  Keunnam KIM ,  Kiseok LEE

    IPC: H10B12/00 ,  H01L29/78

    CPC classification number: H10B12/482 ,  H01L29/7827

    Abstract: A semiconductor device may include a substrate, a bit line structure, first and second gate electrodes spaced apart from each other, and first and second gate dielectric layers. The substrate may include a first upper active region and a second upper active region spaced apart from each other and protruding upwardly from a lower active region, a first vertical active pillar protruding upwardly from the first upper active region, and a second vertical active pillar protruding upwardly from the second upper active region. The bit line structure may be between the first and second upper active regions. The first and second gate electrodes respectively may surround channel regions of the first and second vertical active pillars. First and second gate dielectric layers respectively may be between the first vertical active pillar and the first gate electrode and between the second vertical active pillar and the second gate electrode.

    SEMICONDUCTOR MEMORY DEVICE
    2.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230354588A1

    公开(公告)日：2023-11-02

    申请号：US18117604

    申请日：2023-03-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Junhyeok AHN ,  Keunnam KIM ,  Chan-Sic YOON ,  Myeong-Dong LEE

    IPC: H10B12/00

    CPC classification number: H10B12/485 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/02

    Abstract: A semiconductor memory device includes a semiconductor substrate; a device isolation layer defining an active portion in the semiconductor substrate; a bit line structure intersecting the active portion on the semiconductor substrate; a first conductive pad between the bit line structure and the active portion; a bit line contact pattern between the first conductive pad and the bit line structure; a first bit line contact spacer covering a first sidewall of the first conductive pad; and a second bit line contact spacer covering a second sidewall of the first conductive pad, wherein the first conductive pad has a flat bottom surface that is in contact with a top surface of the active portion, and a width of the first bit line contact spacer is different from a width of the second bit line contact spacer.

    SEMICONDUCTOR DEVICE
    3.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230253318A1

    公开(公告)日：2023-08-10

    申请号：US18062811

    申请日：2022-12-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiseok LEE ,  Chansic YOON ,  Keunnam KIM

    IPC: H01L23/528 ,  H10B12/00

    CPC classification number: H01L23/5283 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/10885 ,  H01L27/10814

    Abstract: A semiconductor device includes a substrate including an active region, a word line structure, a bit line structure on the substrate, and a bit line contact pattern configured to electrically connect a first impurity region of the active region with the bit line structure. The device includes a storage node contact on a side wall of the bit line structure, and the storage node contact is electrically connected to a second impurity region of the active region. The device includes a spacer structure on a side wall of the bit line structure, the spacer structure on a side wall of the bit line contact pattern, the spacer structure including a lower spacer structure surrounding a side surface of the lower portion, and an upper spacer structure disposed on a side surface of the upper portion. The device includes a capacitor structure electrically connected to the storage node contact.

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20230055499A1

    公开(公告)日：2023-02-23

    申请号：US17805706

    申请日：2022-06-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Keunnam KIM ,  Hui-Jung KIM ,  Wonsok LEE ,  Min Hee CHO

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573

    Abstract: A semiconductor memory device may be provided. The semiconductor memory device may include a bit line, a channel pattern on the bit line, the channel pattern including a horizontal channel portion, which is provided on the bit line, and a vertical channel portion, which is vertically extended from the horizontal channel portion, a word line provided on the channel pattern to cross the bit line, the word line including a horizontal portion, which is provided on the horizontal channel portion, and a vertical portion, which is vertically extended from the horizontal portion to face the vertical channel portion, and a gate insulating pattern provided between the channel pattern and the word line.

    SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210408008A1

    公开(公告)日：2021-12-30

    申请号：US17471824

    申请日：2021-09-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L27/24

    Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

    SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200043941A1

    公开(公告)日：2020-02-06

    申请号：US16508839

    申请日：2019-07-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hui-Jung KIM ,  Kiseok LEE ,  Keunnam KIM ,  Yoosang HWANG

    IPC: H01L27/11578 ,  H01L27/1157 ,  H01L27/11573

    Abstract: A semiconductor device may include a stack structure that includes a plurality of layers vertically stacked on a substrate, and a plurality of gate electrodes that vertically extend to penetrate the stack structure. Each of the plurality of layers may include a plurality of semiconductor patterns that extend in parallel along a first direction, a bit line that is electrically connected to the semiconductor patterns and extends in a second direction intersecting the first direction, a first air gap on the bit line, and a data storage element that is electrically connected to a corresponding one of the semiconductor patterns. The first air gap is interposed between the bit line of a first layer of the plurality of layers and the bit line of a second layer of the plurality of layers.

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