公开(公告)号：US11387367B2

公开(公告)日：2022-07-12

申请号：US17034421

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woocheol Shin ,  Sunggi Hur ,  Sangwon Baek ,  Junghan Lee

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are stacked in a vertical direction. Each channel extends in a first direction. The gate structure extends in a second direction. The gate structure covers the channels. The source/drain layer is connected to each of opposite sidewalls in the first direction of the channels on the substrate, and includes a doped semiconductor material. The source/drain layer includes first and second epitaxial layers having first and second impurity concentrations, respectively. The first epitaxial layer covers a lower surface and opposite sidewalls in the first direction of the second epitaxial layer. A portion of each of opposite sidewalls in the first direction of the gate structure protrudes in the first direction from opposite sidewalls in the first direction of the channels to partially penetrate through the first epitaxial layer but not to contact the second epitaxial layer.

公开(公告)号：US20210074701A1

公开(公告)日：2021-03-11

申请号：US16855321

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghan Lee ,  Taeyong Kwon ,  Minchul Sun ,  Byounggi Kim ,  Suhyeon Park ,  Kihwan Lee

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device may include a substrate including first regions and a second region between the first regions. Active fins may protrude from the substrate in the first regions. Each of the active fins may extend in a first direction parallel to an upper surface of the substrate. The active fins may be regularly arranged and spaced apart from each other in a second direction. First trenches may be at both edges of the second region. A protrusion may be between the first trenches. An upper surface of the protrusion may be lower than a bottom of the active fins. A first width in the second direction of one of the first trenches may be greater than 0.7 times a first pitch of the active fins that is a sum of a width of one of the active fins and a distance between adjacent ones of the active fins.

公开(公告)号：US20240128354A1

公开(公告)日：2024-04-18

申请号：US18231549

申请日：2023-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisoo Park ,  Byungju Kang ,  Junghan Lee ,  Jaehyoung Lim

IPC: H01L29/66 ,  H01L23/48

CPC classification number: H01L29/66545 ,  H01L23/481 ,  H01L29/66795

Abstract: In a method of manufacturing a semiconductor device, an alignment key is formed through a portion of a substrate including first and second surfaces opposite to each other, which is adjacent to the second surface of the substrate. A transistor including a gate structure and a source/drain layer is formed on the second surface of the substrate. A portion of the substrate adjacent to the first surface of the substrate is removed to expose the alignment key. A contact plug is formed through a portion of the substrate adjacent to the first surface of the substrate to be electrically connected to the source/drain layer. A power rail is formed on the first surface of the substrate to be electrically connected to the contact plug.

公开(公告)号：US11410997B2

公开(公告)日：2022-08-09

申请号：US16855321

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghan Lee ,  Taeyong Kwon ,  Minchul Sun ,  Byounggi Kim ,  Suhyeon Park ,  Kihwan Lee

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor device may include a substrate including first regions and a second region between the first regions. Active fins may protrude from the substrate in the first regions. Each of the active fins may extend in a first direction parallel to an upper surface of the substrate. The active fins may be regularly arranged and spaced apart from each other in a second direction. First trenches may be at both edges of the second region. A protrusion may be between the first trenches. An upper surface of the protrusion may be lower than a bottom of the active fins. A first width in the second direction of one of the first trenches may be greater than 0.7 times a first pitch of the active fins that is a sum of a width of one of the active fins and a distance between adjacent ones of the active fins.

公开(公告)号：US12261220B2

公开(公告)日：2025-03-25

申请号：US18597440

申请日：2024-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woocheol Shin ,  Sunggi Hur ,  Sangwon Baek ,  Junghan Lee

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are stacked in a vertical direction. Each channel extends in a first direction. The gate structure extends in a second direction. The gate structure covers the channels. The source/drain layer is connected to each of opposite sidewalls in the first direction of the channels on the substrate, and includes a doped semiconductor material. The source/drain layer includes first and second epitaxial layers having first and second impurity concentrations, respectively. The first epitaxial layer covers a lower surface and opposite sidewalls in the first direction of the second epitaxial layer. A portion of each of opposite sidewalls in the first direction of the gate structure protrudes in the first direction from opposite sidewalls in the first direction of the channels to partially penetrate through the first epitaxial layer but not to contact the second epitaxial layer.

公开(公告)号：US11211454B2

公开(公告)日：2021-12-28

申请号：US16821491

申请日：2020-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghan Lee ,  Changhee Kim ,  Kihwan Kim ,  Suhyueon Park ,  Jaehong Choi

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/167 ,  H01L21/8234 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/02 ,  H01L29/12

Abstract: A semiconductor device including an active region protruding from an upper surface of a substrate and extending in a first horizontal direction, at least two gate electrodes extending in a second horizontal direction and crossing the active region, the second horizontal direction crossing the first horizontal direction, a source/drain region in the active region between the gate electrodes may be provided. The source/drain region includes a recess region, an outer doped layer on an inner wall of the recess region, an intermediate doped layer on the outer doped layer, and an inner doped layer on the intermediate doped layer and filling the recess region. One of the outer doped layer or the intermediate doped layer includes antimony, and the inner doped layer includes phosphorous.

公开(公告)号：US11955556B2

公开(公告)日：2024-04-09

申请号：US17836416

申请日：2022-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woocheol Shin ,  Sunggi Hur ,  Sangwon Baek ,  Junghan Lee

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are stacked in a vertical direction. Each channel extends in a first direction. The gate structure extends in a second direction. The gate structure covers the channels. The source/drain layer is connected to each of opposite sidewalls in the first direction of the channels on the substrate, and includes a doped semiconductor material. The source/drain layer includes first and second epitaxial layers having first and second impurity concentrations, respectively. The first epitaxial layer covers a lower surface and opposite sidewalls in the first direction of the second epitaxial layer. A portion of each of opposite sidewalls in the first direction of the gate structure protrudes in the first direction from opposite sidewalls in the first direction of the channels to partially penetrate through the first epitaxial layer but not to contact the second epitaxial layer.

公开(公告)号：US20240194521A1

公开(公告)日：2024-06-13

申请号：US18533635

申请日：2023-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisoo PARK ,  Junghan Lee ,  Kwanyoung Chun

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/7684 ,  H01L21/76877

Abstract: A method of forming a pattern of a semiconductor device, the method comprising forming an insulating film on a substrate having a first region and a second region, sequentially forming a lower mask layer and an upper mask layer on the insulating film, forming a line-shaped hard mask pattern having a plurality of narrow openings having the same width in the first region and the second region, respectively, on the upper mask layer, forming line-shaped spacers on sidewalls of the opening of the line-shaped hard mask pattern, forming a composite mask pattern composed of the spacer and a pattern having a first width among the line-shaped hard mask pattern by removing a pattern having a second width among the line-shaped hard mask patterns, the second width being smaller than the first width.

公开(公告)号：US11682698B2

公开(公告)日：2023-06-20

申请号：US17541878

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghan Lee ,  Changhee Kim ,  Kihwan Kim ,  Suhyueon Park ,  Jaehong Choi

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/167 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/36

CPC classification number: H01L29/0847 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device including an active region protruding from an upper surface of a substrate and extending in a first horizontal direction, at least two gate electrodes extending in a second horizontal direction and crossing the active region, the second horizontal direction crossing the first horizontal direction, a source/drain region in the active region between the gate electrodes may be provided. The source/drain region includes a recess region, an outer doped layer on an inner wall of the recess region, an intermediate doped layer on the outer doped layer, and an inner doped layer on the intermediate doped layer and filling the recess region. One of the outer doped layer or the intermediate doped layer includes antimony, and the inner doped layer includes phosphorous.