公开(公告)号：US11741596B2

公开(公告)日：2023-08-29

申请号：US16599733

申请日：2019-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul Park ,  Ami Ma ,  Jisu Ryu ,  Changwook Jeong

IPC: G06K9/00 ,  G06T7/00 ,  H01L21/67 ,  G01N21/956 ,  G01N21/95 ,  G06T5/00 ,  G01N21/88 ,  G06V10/70 ,  G06V10/82 ,  G06V10/74

CPC classification number: G06T7/001 ,  G01N21/8851 ,  G01N21/9501 ,  G01N21/95607 ,  G06T5/002 ,  G06T7/0004 ,  G06V10/70 ,  G06V10/74 ,  G06V10/82 ,  H01L21/67288 ,  G01N2021/8854 ,  G01N2021/8867 ,  G01N2021/95615 ,  G06T2207/20081 ,  G06T2207/30141 ,  G06T2207/30148

Abstract: A semiconductor wafer fault analysis system includes: a database to store a first reference map, which is classified as a first fault type, and a second reference map, which is classified as a second fault type; a first auto-encoder/decoder to remove a noise corresponding to the first fault type from the first reference map to generate a first pre-processed reference map; a second auto-encoder/decoder to remove a noise corresponding to the second fault type from the second reference map to generate a second pre-processed reference map; and a fault type analyzer. The database is updated based on the first and second pre-processed reference maps, and the fault type analyzer is to classify a fault type of a target map based on the updated database. The target map is generated by measuring a target wafer.

公开(公告)号：US09882120B2

公开(公告)日：2018-01-30

申请号：US14956766

申请日：2015-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin Ahn ,  Jisu Ryu

IPC: H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/228 ,  H01L43/12

Abstract: A magnetic memory device can include an upper electrode, a lower electrode and a Magnetic Tunnel Junction (MTJ). The MTJ can include a reference magnetic pattern configured to generate a fixed magnetization and a free magnetic pattern on the reference magnetic pattern configured to generate a switchable magnetization that switches direction between parallel and anti-parallel to the fixed magnetization. A metal pattern can be on the free magnetic pattern and can be configured to conduct an in-plane current and a perpendicular-to-plane to/from the upper electrode.

公开(公告)号：US11994562B2

公开(公告)日：2024-05-28

申请号：US17309295

申请日：2019-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sengtai Lee ,  Daejin Kwak ,  Jisu Ryu ,  Yonghyun Park ,  Jinhyuk Choi ,  Yonghwan Hyun

IPC: G01R31/3835 ,  G01R31/392 ,  H02J7/00 ,  G01R31/36

CPC classification number: G01R31/3835 ,  G01R31/392 ,  H02J7/0029 ,  H02J7/0049 ,  G01R31/3646

Abstract: Various embodiments of the present invention relate to an electronic device for diagnosing a battery, and the electronic device may include a battery; and a power management module operatively connected with the battery, and including a charging circuit which controls charge of the battery, wherein the power management module is configured to monitor a charge state of the battery, if the battery reaches a first designated state, identify a time taken to change from the first designated state to a second designated state, and determine whether the battery is abnormal, based at least in part on the identified time. Other various embodiments are possible.

公开(公告)号：US10650910B2

公开(公告)日：2020-05-12

申请号：US16249543

申请日：2019-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changwook Jeong ,  Sanghoon Myung ,  Min-Chul Park ,  Jeonghoon Ko ,  Jisu Ryu ,  Hyunjae Jang ,  Hyungtae Kim ,  Yunrong Li ,  Min Chul Jeon

IPC: G11C7/00 ,  G11C29/50 ,  G11C29/48 ,  G11C29/56 ,  G01R31/27 ,  G01R31/3185 ,  G01R31/30 ,  G01R31/26

Abstract: A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.

公开(公告)号：US20220207393A1

公开(公告)日：2022-06-30

申请号：US17468819

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Naoto Umezawa ,  Changwook Jeong ,  Jisu Ryu ,  Kyu Hyun Lee ,  Jinyoung Lim ,  Wonik Jang ,  In Huh

IPC: G06N5/04 ,  G06N5/02

Abstract: Disclosed are methods of predicting semiconductor material properties and methods of testing semiconductor devices using the same. The prediction method comprises preparing a machine learning model that is trained with a training system and using the machine learning model to predict material properties of a target system. The machine learning model is represented as a function of material properties with respect to a descriptor. The descriptor is calculated from unrelaxed charge density (UCD) that is represented by summation of atomic charge density (ACD) of single atoms.

公开(公告)号：US12236178B2

公开(公告)日：2025-02-25

申请号：US17503558

申请日：2021-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yohan Kim ,  Changwook Jeong ,  Jisu Ryu

IPC: G06F30/367 ,  G06F18/20 ,  G06F119/06 ,  G06N7/01

Abstract: A method of generating a circuit model used to simulate an integrated circuit may include generating first feature element data and second feature element data by classifying feature data of a target semiconductor device according to measurement conditions, generating first target data and second target data by preprocessing the first feature element data and the second feature element data, respectively, generating a first machine learning model using the first target data and extracting a second machine learning model using the second target data, and generating the circuit model used to simulate the integrated circuit using the first machine learning model and the second machine learning model.

公开(公告)号：US11982980B2

公开(公告)日：2024-05-14

申请号：US17230275

申请日：2021-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Kim ,  Sanghoon Myung ,  Wonik Jang ,  Yongwoo Jeon ,  Kanghyun Baek ,  Jisu Ryu ,  Changwook Jeong

IPC: G05B13/04 ,  G05B13/02 ,  G06N3/045 ,  H01L27/02

CPC classification number: G05B13/042 ,  G05B13/027 ,  G06N3/045 ,  H01L27/0207

Abstract: According to an aspect of the present inventive concept, a simulation method for a semiconductor fabrication process includes obtaining, as input data, process parameters for controlling a semiconductor process of manufacturing semiconductor devices, or design parameters representing a structure of the semiconductor devices, or both the process parameters and the design parameters; generating predictive data for electrical characteristics of the semiconductor devices using a machine learning model based on the input data; generating reference data for the electrical characteristics of the semiconductor devices using a simulation tool based on the input data; and training the machine learning model using the predictive data and the reference data.

公开(公告)号：US20220121800A1

公开(公告)日：2022-04-21

申请号：US17503558

申请日：2021-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yohan Kim ,  Changwook Jeong ,  Jisu Ryu

IPC: G06F30/367 ,  G06N7/00 ,  G06K9/62

Abstract: A method of generating a circuit model used to simulate an integrated circuit may include generating first feature element data and second feature element data by classifying feature data of a target semiconductor device according to measurement conditions, generating first target data and second target data by preprocessing the first feature element data and the second feature element data, respectively, generating a first machine learning model using the first target data and extracting a second machine learning model using the second target data, and generating the circuit model used to simulate the integrated circuit using the first machine learning model and the second machine learning model.