公开(公告)号：US20220207393A1

公开(公告)日：2022-06-30

申请号：US17468819

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Naoto Umezawa ,  Changwook Jeong ,  Jisu Ryu ,  Kyu Hyun Lee ,  Jinyoung Lim ,  Wonik Jang ,  In Huh

IPC: G06N5/04 ,  G06N5/02

Abstract: Disclosed are methods of predicting semiconductor material properties and methods of testing semiconductor devices using the same. The prediction method comprises preparing a machine learning model that is trained with a training system and using the machine learning model to predict material properties of a target system. The machine learning model is represented as a function of material properties with respect to a descriptor. The descriptor is calculated from unrelaxed charge density (UCD) that is represented by summation of atomic charge density (ACD) of single atoms.

公开(公告)号：US11696436B2

公开(公告)日：2023-07-04

申请号：US17035082

申请日：2020-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Seok Lee ,  Jae Hyun Yoon ,  Kyu Jin Kim ,  Keun Nam Kim ,  Hui-Jung Kim ,  Kyu Hyun Lee ,  Sang-Il Han ,  Sung Hee Han ,  Yoo Sang Hwang

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053

Abstract: A includes an element isolation region, a first active region bounded by the element isolation region and that extends in a first direction and includes first and second parts disposed at a first level, and a third part disposed at a second level located above the first level, and a gate electrode disposed inside each of the element isolation region and the first active region and that extends in a second direction different from the first direction. The second part is spaced apart in the first direction from the first part, and the third part contacts each of the first and second parts. A first width in the second direction of the first part is less than a second width in the second direction of the third part.

公开(公告)号：US11239311B2

公开(公告)日：2022-02-01

申请号：US16897492

申请日：2020-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hui-Jung Kim ,  Kyu Jin Kim ,  Sang-Il Han ,  Kyu Hyun Lee ,  Woo Young Choi ,  Yoo Sang Hwang

IPC: H01L29/06 ,  H01L29/423

Abstract: A semiconductor device including a device isolation layer defining an active region; a first trench in the device isolation layer; a second trench in the active region; a main gate electrode structure filling a portion of the first trench and including a first barrier conductive layer and a main gate electrode; a pass gate electrode structure filling a portion of the second trench and including a second barrier conductive layer and a pass gate electrode; a support structure filling another portion of the second trench above the pass gate electrode; a first capping pattern filling another portion of the first trench above the main gate electrode; and a second gate insulating layer extending along a bottom and sidewall of the second trench, wherein the second barrier conductive layer is between the second gate insulating layer and the pass gate electrode and extends along a bottom and sidewall thereof.

公开(公告)号：US11715760B2

公开(公告)日：2023-08-01

申请号：US17587444

申请日：2022-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hui-Jung Kim ,  Kyu Jin Kim ,  Sang-Il Han ,  Kyu Hyun Lee ,  Woo Young Choi ,  Yoo Sang Hwang

IPC: H01L29/06 ,  H01L29/423

CPC classification number: H01L29/0649 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/42368

Abstract: A semiconductor device including a device isolation layer defining an active region; a first trench in the device isolation layer; a second trench in the active region; a main gate electrode structure filling a portion of the first trench and including a first barrier conductive layer and a main gate electrode; a pass gate electrode structure filling a portion of the second trench and including a second barrier conductive layer and a pass gate electrode; a support structure filling another portion of the second trench above the pass gate electrode; a first capping pattern filling another portion of the first trench above the main gate electrode; and a second gate insulating layer extending along a bottom and sidewall of the second trench, wherein the second barrier conductive layer is between the second gate insulating layer and the pass gate electrode and extends along a bottom and sidewall thereof.