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    Layout method
    1.
    发明授权
    Layout method 有权

    公开(公告)号：US11094693B2

    公开(公告)日：2021-08-17

    申请号：US16255519

    申请日：2019-01-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： In Wook Oh ,  Jae Seok Yang ,  Jong Hyun Lee ,  Hyun Jae Lee ,  Sung Wook Hwang

    IPC: H01L27/088 ,  G06F30/39 ,  G06F30/392 ,  H01L23/528 ,  H01L27/02

    Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.

    Integrated circuit (IC) devices including cross gate contacts
    4.
    发明授权
    Integrated circuit (IC) devices including cross gate contacts 有权

    公开(公告)号：US10546855B2

    公开(公告)日：2020-01-28

    申请号：US15473913

    申请日：2017-03-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Rajeev Ranjan ,  Deepak Sharma ,  Subhash Kuchanuri ,  Chul Hong Park ,  Jae Seok Yang ,  Kwan Young Chun

    IPC: H01L27/088 ,  H01L23/528 ,  H01L27/02 ,  H01L29/06 ,  H01L27/092 ,  H01L23/522

    Abstract: Integrated circuit devices are provided. The IC devices may include an active region extending in a first direction, first and second gate electrodes extending in a second direction, a first impurity region in the active region adjacent a first side of the first gate electrode, a second impurity region in the active region between a second side of the first gate electrode and a first side of the second gate electrode, a third impurity region in the active region adjacent a second side of the second gate electrode, a cross gate contact electrically connecting the first and second impurity regions, a first contact electrically connected to the third impurity region, a first wire electrically connected to the cross gate contact, and a second wire electrically connected to the first contact. The first and second wires may extend only in the first direction and may be on the same line.

    Semiconductor devices with insulated source/drain jumper structures
    5.
    发明授权
    Semiconductor devices with insulated source/drain jumper structures 有权

    公开(公告)号：US10699998B2

    公开(公告)日：2020-06-30

    申请号：US15936882

    申请日：2018-03-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sidharth Rastogi ,  Subhash Kuchanuri ,  Jae Seok Yang ,  Kwan Young Chun

    IPC: H01L23/522 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12

    Abstract: A semiconductor device includes an insulator on a substrate and having opposite first and second sides that each extend along a first direction, a first fin pattern extending from a third side of the insulator along the first direction, a second fin pattern extending from a fourth side of the insulator along the first direction, and a first gate structure extending from the first side of the insulator along a second direction transverse to the first direction. The device further includes a second gate structure extending from the second side of the insulator along the second direction, a third fin pattern overlapped by the first gate structure, spaced apart from the first side of the insulator, and extending along the first direction, and a fourth fin pattern which overlaps the second gate structure, is spaced apart from the second side, and extends in the direction in which the second side extends. An upper surface of the insulator is higher than an upper surface of the first fin pattern and an upper surface of the second fin pattern.

    Method for manufacturing a semiconductor device
    6.
    发明授权
    Method for manufacturing a semiconductor device 有权

    公开(公告)号：US09812356B2

    公开(公告)日：2017-11-07

    申请号：US15405762

    申请日：2017-01-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung Wook Hwang ,  Jong Hyun Lee ,  Jae Seok Yang ,  In Wook Oh ,  Hyun Jae Lee

    IPC: H01L23/528 ,  H01L21/768 ,  G06F17/50

    CPC classification number: H01L21/0337 ,  H01L21/76802 ,  H01L23/481

    Abstract: A method for manufacturing a semiconductor device includes generating a layout including a first conductive pattern region and a second conductive pattern region. A first interlayer insulating film is formed on a substrate, the first interlayer insulating film including a first region corresponding to the first conductive pattern region, a second region corresponding to the second conductive pattern region, and a third region spaced apart from the first and second regions and disposed between the first and second regions. First, second and third lower metal wirings are formed to respectively fill the first, second and third recesses of the first interlayer insulating film. A second interlayer insulating film is formed on the first interlayer insulating film. A first dummy via hole is formed in the second interlayer insulating film to expose the third lower metal wiring. The third lower metal wiring is electrically isolated.

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12261201B2

    公开(公告)日：2025-03-25

    申请号：US18499436

    申请日：2023-11-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Hun Kim ,  Jae Seok Yang ,  Hae Wang Lee

    IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

    Abstract: A semiconductor device is provided. The semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11195910B2

    公开(公告)日：2021-12-07

    申请号：US16214659

    申请日：2018-12-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Hun Kim ,  Jae Seok Yang ,  Hae Wang Lee

    IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

    Abstract: A semiconductor device is provided. The semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.

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