公开(公告)号：US09812356B2

公开(公告)日：2017-11-07

申请号：US15405762

申请日：2017-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Wook Hwang ,  Jong Hyun Lee ,  Jae Seok Yang ,  In Wook Oh ,  Hyun Jae Lee

IPC: H01L23/528 ,  H01L21/768 ,  G06F17/50

CPC classification number: H01L21/0337 ,  H01L21/76802 ,  H01L23/481

Abstract: A method for manufacturing a semiconductor device includes generating a layout including a first conductive pattern region and a second conductive pattern region. A first interlayer insulating film is formed on a substrate, the first interlayer insulating film including a first region corresponding to the first conductive pattern region, a second region corresponding to the second conductive pattern region, and a third region spaced apart from the first and second regions and disposed between the first and second regions. First, second and third lower metal wirings are formed to respectively fill the first, second and third recesses of the first interlayer insulating film. A second interlayer insulating film is formed on the first interlayer insulating film. A first dummy via hole is formed in the second interlayer insulating film to expose the third lower metal wiring. The third lower metal wiring is electrically isolated.

公开(公告)号：US10217742B2

公开(公告)日：2019-02-26

申请号：US15902025

申请日：2018-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In Wook Oh ,  Jae Seok Yang ,  Jong Hyun Lee ,  Hyun Jae Lee ,  Sung Wook Hwang

IPC: H01L27/08 ,  H01L27/02 ,  H01L23/52 ,  G06F17/50 ,  H01L27/088 ,  H01L23/528

Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.

公开(公告)号：US10923420B2

公开(公告)日：2021-02-16

申请号：US15873352

申请日：2018-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： In Wook Oh ,  Dong Hyun Kim ,  Doo Hwan Park ,  Sung Keun Park ,  Chul Hong Park ,  Sung Wook Hwang

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L23/532 ,  H01L21/285

Abstract: A semiconductor device includes a plurality of main contact plugs and a plurality of dummy contact plugs which pass through an insulating layer on a substrate. A plurality of upper interconnections is on the insulating layer. The plurality of dummy contact plugs include a first dummy contact plug. The plurality of upper interconnections include a first upper interconnection overlapping the first dummy contact plug. A vertical central axis of the first dummy contact plug is located outside the first upper interconnection.

公开(公告)号：US11094693B2

公开(公告)日：2021-08-17

申请号：US16255519

申请日：2019-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In Wook Oh ,  Jae Seok Yang ,  Jong Hyun Lee ,  Hyun Jae Lee ,  Sung Wook Hwang

IPC: H01L27/088 ,  G06F30/39 ,  G06F30/392 ,  H01L23/528 ,  H01L27/02

Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.

公开(公告)号：US09929156B2

公开(公告)日：2018-03-27

申请号：US15372840

申请日：2016-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In Wook Oh ,  Jae Seok Yang ,  Jong Hyun Lee ,  Hyun Jae Lee ,  Sung Wook Hwang

IPC: H01L27/08 ,  H01L27/02 ,  H01L23/52 ,  H01L29/66 ,  G06F17/50 ,  H01L27/088 ,  H01L23/528

CPC classification number: H01L27/0886 ,  G06F17/5072 ,  H01L23/528 ,  H01L27/0207

Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.