公开(公告)号：US20210119036A1

公开(公告)日：2021-04-22

申请号：US17119507

申请日：2020-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Kwan YU ,  Sung-Min KIM ,  Dong-Suk SHIN ,  Seung-Hun LEE ,  Dong-Won KIM

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/11 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device may include a first active fin, a second active fin and a gate structure. The first active fin may extend in a first direction on a substrate and may include a first straight line extension portion, a second straight line extension portion, and a bent portion between the first and second straight line extension portions. The second active fin may extend in the first direction on the substrate. The gate structure may extend in a second direction perpendicular to the first direction on the substrate. The gate structure may cross one of the first and second straight line extension portions of the first active fin and may cross the second active fin.

公开(公告)号：US20190081168A1

公开(公告)日：2019-03-14

申请号：US16045305

申请日：2018-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Kwan YU ,  Sung-Min KIM ,  Dong-Suk SHIN ,  Seung-Hun LEE ,  Dong-Won KIM

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L27/11

Abstract: A semiconductor device may include a first active fin, a second active fin and a gate structure. The first active fin may extend in a first direction on a substrate and may include a first straight line extension portion, a second straight line extension portion, and a bent portion between the first and second straight line extension portions. The second active fin may extend in the first direction on the substrate. The gate structure may extend in a second direction perpendicular to the first direction on the substrate. The gate structure may cross one of the first and second straight line extension portions of the first active fin and may cross the second active fin.

公开(公告)号：US20250081559A1

公开(公告)日：2025-03-06

申请号：US18624201

申请日：2024-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunyoung LEE ,  Hyun-Kwan YU ,  Hyojin KIM

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern including a first semiconductor pattern and a second semiconductor pattern, a source/drain pattern connected to the first and second semiconductor patterns, and a gate electrode including an electrode between the first and second semiconductor patterns, and an insulating layer between the first and second semiconductor patterns and the electrode. The insulating layer includes a dielectric layer enclosing the electrode and a spacer on the dielectric layer. The spacer includes a horizontal portion between the dielectric layer and the second semiconductor pattern, a vertical portion between the dielectric layer and the source/drain pattern, and a corner portion connecting the horizontal portion to the vertical portion. A first thickness of the horizontal portion is smaller than a second thickness of the vertical portion, and the second thickness is smaller than a third thickness of the corner portion.

公开(公告)号：US20240055428A1

公开(公告)日：2024-02-15

申请号：US18182563

申请日：2023-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Kwan YU ,  Sunyoung LEE ,  Hayoung JEON ,  Hwiseok JUN ,  Ji Hoon CHA

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/775 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66439

Abstract: A semiconductor device comprises a substrate including NMOSFET and PMOSFET regions, first and second channel patterns on the NMOSFET and PMOSFET regions, respectively, and each including respective semiconductor patterns spaced apart from and vertically stacked on each other, first and second source/drain patterns on the NMOSFET and NMOSFET regions and connected to the first and second channel patterns, respectively, and a gate electrode on the first and second channel patterns. The gate electrode includes a first inner electrode between neighboring semiconductor patterns of the first channel pattern, and a second inner electrode between neighboring semiconductor patterns of the second channel pattern. A top surface of the first inner electrode is more convex than a top surface of the second inner electrode.

公开(公告)号：US20240194786A1

公开(公告)日：2024-06-13

申请号：US18531898

申请日：2023-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Suk SHIN ,  Jung Taek KIM ,  Hyun-Kwan YU ,  Seok Hoon KIM ,  Pan Kwi PARK ,  Seo Jin JEONG ,  Nam Kyu CHO

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7855 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/66545

Abstract: There is provided a semiconductor device capable of improving performance and reliability of an element. The semiconductor device includes an active pattern extending in a first direction, and a plurality of gate structures spaced apart from each other in the first direction on the active pattern. Each gate structure comprises a gate electrode extending in a second direction and a gate spacer on a sidewall of the gate electrode and a source/drain pattern disposed between adjacent gate structures. The gate structure comprises a semiconductor liner layer and a semiconductor filling layer on the semiconductor liner layer, wherein the semiconductor liner layer and the semiconductor filling layer are formed of silicon-germanium. The semiconductor filling layer comprises an upper portion protruding in a third direction beyond an upper surface of the active pattern. A maximum width of the upper portion of the semiconductor filling layer in the first direction is greater than a width of the semiconductor filling layer in the first direction on the upper surface of the active pattern. The semiconductor liner layer comprises an outer surface in contact with the active pattern and an inner surface facing the semiconductor filling layer. In a plan view, the inner surface of the semiconductor liner layer comprises a concave region.

公开(公告)号：US20200342157A1

公开(公告)日：2020-10-29

申请号：US16794045

申请日：2020-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alexander SCHMIDT ,  Dong-Gwan SHIN ,  Anthony PAYET ,  Hyoung Soo KO ,  Seok Hoon KIM ,  Hyun-Kwan YU ,  Si Hyung LEE ,  In Kook JANG

IPC: G06F30/398 ,  H01L27/02 ,  G06F30/367

Abstract: A simulation method and system which can determine a predictable epitaxy time by accurately reflecting layout characteristics of a chip and characteristics of a source/drain formation process are provided. The simulation method includes storing a plurality of structure parameters of transistors for a semiconductor chip, the structure parameters determined by using imaging equipment, generating a first local layout which includes a first structure parameter extracted from a semiconductor device included in the first local layout, the first structure parameter being an actual parameter determined using the imaging equipment, generating second to n-th local layouts by modifying the first structure parameter included in the first local layout, wherein the second to n-th local layouts respectively have second to n-th structure parameters modified from the first structure parameter, calculating first to n-th effective density factors(EDF) respectively for the first to n-th structure parameters using a predetermined simulation of the first to n-th structure parameters, determining a first effective open silicon density for a first chip using the first to n-th effective density factors and a layout of the first chip, and calculating a first epitaxy time for the first effective open silicon density, calculating second to m-th epitaxy times for second to m-th effective open silicon densities, and performing a regression analysis of effective open silicon density versus epitaxy time based on the calculation result, where n is a natural number equal to or greater than 3, and m is a natural number equal to or greater than 3.

公开(公告)号：US20170194158A1

公开(公告)日：2017-07-06

申请号：US15398776

申请日：2017-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Kwan YU ,  Woonki SHIN ,  Moonhan PARK ,  DongSuk SHIN ,  HanJin LIM

IPC: H01L21/306 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/30604 ,  H01L21/02057 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481

Abstract: An etching method is disclosed. The etching method comprises providing on a substrate a structure comprising a recess region formed therein. The recess region includes an inner part and a mouth part whose width is less than that of the inner part. The etching method further comprises performing a clean-then-etch process to remove at least a portion of etching object formed outside the recess region. The performing a clean-then-etch process comprises performing a cleaning process to fill at least a portion of the recess region with a cleaning solution, and performing a wet etch process to the substrate in a state that the cleaning solution remains in the recess region.