公开(公告)号：US20200303538A1

公开(公告)日：2020-09-24

申请号：US16894270

申请日：2020-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggil YANG ,  Seungmin SONG ,  Geumjong BAE ,  Dong Il BAE

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

公开(公告)号：US20220173214A1

公开(公告)日：2022-06-02

申请号：US17371582

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Noh Yeong PARK ,  Dong Il BAE ,  Beomjin PARK

IPC: H01L29/10 ,  H01L27/092 ,  H01L29/16 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8238

Abstract: Disclosed are semiconductor devices and/or method of fabricating the same. The semiconductor device comprises a substrate including first and second regions, a first active pattern on the first region and including a pair of first source/drain patterns and a first channel pattern including first semiconductor patterns, a second active pattern on the second region and including a pair of second source/drain patterns and a second channel pattern including second semiconductor patterns, a support pattern between two vertically adjacent first semiconductor patterns, and a first gate electrode and a second gate electrode on the first channel pattern and the second channel pattern. A channel length of the first channel pattern is greater than that of the second channel pattern. A ratio of a width of the support pattern to the channel length of the first channel pattern is in a range of 0.05 to 0.2.

公开(公告)号：US20200373402A1

公开(公告)日：2020-11-26

申请号：US16732520

申请日：2020-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil YANG ,  Seung Min SONG ,  Soo Jin JEONG ,  Dong Il BAE ,  Bong Seok SUH

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L27/092

Abstract: A semiconductor device having a gate-all-around structure includes a first fin pattern and a second fin pattern separated by a first trench and extending in a first direction, a first nanosheet on the first fin pattern, a second nanosheet on the second fin pattern, a first fin liner extending along at least a portion of a sidewall and a bottom surface of the first trench, a first field insulation layer disposed on the first fin liner and filling a portion of the first trench, and a first gate structure overlapping an end portion of the first fin pattern and including a first gate spacer. A height from the bottom surface of the first trench to a lower surface of the first gate spacer is greater than a height from the bottom surface of the first trench to an upper surface of the first field insulation layer.

公开(公告)号：US20220310852A1

公开(公告)日：2022-09-29

申请号：US17840737

申请日：2022-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Woo Seok PARK ,  Dong Chan SUH ,  Seung Min SONG ,  Geum Jong BAE ,  Dong Il BAE

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/10 ,  H01L29/161 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/06

Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.

公开(公告)号：US20220262790A1

公开(公告)日：2022-08-18

申请号：US17466043

申请日：2021-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jun KIM ,  Beomjin PARK ,  Dong Il BAE ,  Mirco CANTORO

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/423

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The semiconductor device includes a plurality of gate structures that are spaced apart from each other in a first direction on a substrate and extend in a second direction intersecting the first direction, and a plurality of separation patterns penetrating immediately neighboring ones of the plurality of gate structures, respectively. Each of the plurality of separation patterns separates a corresponding one of the neighboring gate structures into a pair of gate structures that are spaced apart from each other in the second direction. The plurality of separation patterns are spaced apart from and aligned with each other along the first direction.

公开(公告)号：US20190088789A1

公开(公告)日：2019-03-21

申请号：US16161765

申请日：2018-10-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Min SONG ,  Woo Seok PARK ,  Geum Jong BAE ,  Dong Il BAE ,  Jung Gil YANG

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/423

Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.

公开(公告)号：US20240387527A1

公开(公告)日：2024-11-21

申请号：US18786756

申请日：2024-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jun KIM ,  Beomjin PARK ,  Dong Il BAE ,  Mirco CANTORO

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/423

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The semiconductor device includes a plurality of gate structures that are spaced apart from each other in a first direction on a substrate and extend in a second direction intersecting the first direction, and a plurality of separation patterns penetrating immediately neighboring ones of the plurality of gate structures, respectively. Each of the plurality of separation patterns separates a corresponding one of the neighboring gate structures into a pair of gate structures that are spaced apart from each other in the second direction. The plurality of separation patterns are spaced apart from and aligned with each other along the first direction.

公开(公告)号：US20240204054A1

公开(公告)日：2024-06-20

申请号：US18589893

申请日：2024-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Noh Yeong PARK ,  Dong Il BAE ,  Beomjin PARK

IPC: H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/1033 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41775 ,  H01L29/42364 ,  H01L29/42372

Abstract: Disclosed are semiconductor devices and/or method of fabricating the same. The semiconductor device comprises a substrate including first and second regions, a first active pattern on the first region and including a pair of first source/drain patterns and a first channel pattern including first semiconductor patterns, a second active pattern on the second region and including a pair of second source/drain patterns and a second channel pattern including second semiconductor patterns, a support pattern between two vertically adjacent first semiconductor patterns, and a first gate electrode and a second gate electrode on the first channel pattern and the second channel pattern. A channel length of the first channel pattern is greater than that of the second channel pattern. A ratio of a width of the support pattern to the channel length of the first channel pattern is in a range of 0.05 to 0.2.

公开(公告)号：US20210104613A1

公开(公告)日：2021-04-08

申请号：US17127230

申请日：2020-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Woo NOH ,  Seung Min SONG ,  Geum Jong BAE ,  Dong Il BAE

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.

公开(公告)号：US20210035976A1

公开(公告)日：2021-02-04

申请号：US16919300

申请日：2020-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeong Han GWON ,  Soo Yeon JEONG ,  Geum Jong BAE ,  Dong Il BAE

IPC: H01L27/092 ,  H01L23/535 ,  H01L29/423

Abstract: A semiconductor device includes a substrate, a first lower pattern and a second lower pattern on the substrate and arranged in a line in a first direction, a first active pattern stack disposed on and spaced apart from the first lower pattern, a second active pattern stack disposed on and spaced apart from the first lower pattern, a fin-cut gate structure disposed on the first lower pattern and overlapping a portion of the first lower pattern, a first gate structure surrounding the first active pattern stack and extending in a second direction crossing the first direction, a second gate structure surrounding the second active pattern stack and extending in the second direction, and a device isolation layer between the first gate structure and the second gate structure and separating the first lower pattern and the second lower pattern.