公开(公告)号：US20220262790A1

公开(公告)日：2022-08-18

申请号：US17466043

申请日：2021-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jun KIM ,  Beomjin PARK ,  Dong Il BAE ,  Mirco CANTORO

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/423

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The semiconductor device includes a plurality of gate structures that are spaced apart from each other in a first direction on a substrate and extend in a second direction intersecting the first direction, and a plurality of separation patterns penetrating immediately neighboring ones of the plurality of gate structures, respectively. Each of the plurality of separation patterns separates a corresponding one of the neighboring gate structures into a pair of gate structures that are spaced apart from each other in the second direction. The plurality of separation patterns are spaced apart from and aligned with each other along the first direction.

公开(公告)号：US20170092730A1

公开(公告)日：2017-03-30

申请号：US15165145

申请日：2016-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Jun KIM ,  Sung-Dae SUK

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/51

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L28/00 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78645

Abstract: A semiconductor device includes a semiconductor pattern on a substrate along a first direction, a blocking pattern on a top surface of the semiconductor pattern, a first wire pattern on the blocking pattern along a second direction different from the first direction, the first wire including a first part and a second part on opposite sides of the first part, a gate electrode surrounding the first part of the first wire pattern, and a contact surrounding the second part of the first wire pattern, wherein a height of a bottom surface of the contact from a top surface of the substrate is different from a height of a bottom surface of the gate electrode from the top surface of the substrate.

公开(公告)号：US20220130957A1

公开(公告)日：2022-04-28

申请号：US17333080

申请日：2021-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Jun KIM ,  Woong Sik NAM ,  Mirco CANTORO

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device includes first and second active patterns, a field insulating film between the first and second active patterns, a first gate structure intersecting the first active pattern and including a first gate electrode and a first gate spacer, a second gate structure intersecting the second active pattern and including a second gate electrode and a second gate spacer, a gate separation structure on the field insulating film between the first and second gate structures, the gate separation structure including a gate separation filling film on a gate separation liner, and a connecting spacer between the gate separation structure and the field insulating film, the connecting spacer protruding from a top surface of the field insulating film, and the gate separation liner contacting the connecting spacer and extending along a top surface and sidewalls of the connecting spacer and along the top surface of the field insulating film.

公开(公告)号：US20140251776A1

公开(公告)日：2014-09-11

申请号：US14104229

申请日：2013-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jun KIM ,  Jung-Hoon PARK

IPC: H01H13/66 ,  H01H13/50

CPC classification number: H01H13/66 ,  H01H13/702 ,  H01H2003/0293 ,  H01H2231/022 ,  H01H2239/006 ,  H01H2239/074

Abstract: An electronic device includes a substrate having a key sensor region and a touch sensor regions, a dome key unit, a key button, and a touch sensor. The dome key unit is arranged on the key sensor region of the substrate. The key button is arranged above the dome key unit in alignment with the dome key unit. The touch sensor is arranged on the touch sensor region of the substrate. The touch sensor is arranged such that it includes a region overlapping with a part of the key button. The key button can perform at least two functions associated with different input schemes at the same input point of the key button by means of the dome key unit and the touch sensor.

Abstract translation: 电子设备包括具有键传感器区域和触摸传感器区域的基板，圆顶键单元，按键按钮和触摸传感器。 圆顶键单元布置在基板的键传感器区域上。 键按钮配置在圆顶键单元的上方，与圆顶键单元对齐。 触摸传感器设置在基板的触摸传感器区域上。 触摸传感器被布置成使得其包括与键按钮的一部分重叠的区域。 键按钮可以通过穹顶键单元和触摸传感器在键按钮的相同输入点处执行与不同输入方案相关联的至少两个功能。

公开(公告)号：US20130248990A1

公开(公告)日：2013-09-26

申请号：US13718138

申请日：2012-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Jun KIM ,  Hae-Wang LEE ,  Chul-Hong PARK ,  Dong-Kyun SOHN ,  Jong-Shik YOON

IPC: H01L23/538 ,  H01L29/78

CPC classification number: H01L23/5384 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices, and a method for fabricating the same, include an interlayer dielectric film pattern over a substrate, a first wiring within the interlayer dielectric film pattern and having a first length in a first direction, a second wiring within the interlayer dielectric film pattern and separated from the first wiring, and a spacer contacting the first wiring and the second wiring. The spacer electrically separates the first wiring and the second wiring from each other. The second wiring has a second length different from the first length in the first direction.

Abstract translation: 半导体器件及其制造方法包括在衬底上的层间电介质膜图案，层间电介质膜图案内的第一布线，并且具有第一方向的第一长度，层间电介质膜图案内的第二布线和 与第一布线分离，以及与第一布线和第二布线接触的间隔件。 间隔件将第一布线和第二布线彼此电分离。 第二布线具有与第一方向上的第一长度不同的第二长度。

公开(公告)号：US20240178225A1

公开(公告)日：2024-05-30

申请号：US18433753

申请日：2024-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jun KIM ,  Hyungjin PARK

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481

Abstract: A semiconductor device including a substrate; gate structures spaced apart from each other on the substrate, each gate structure including a gate electrode and a gate capping pattern; source/drain patterns on opposite sides of the gate structures; first isolation patterns that respectively penetrate adjacent gate structures; and a second isolation pattern that extends between adjacent source/drain patterns, and penetrates at least one gate structure, wherein each first isolation pattern separates the gate structures such that the gate structures are spaced apart from each other, the first isolation patterns are aligned with each other, and top surfaces of the first and second isolation patterns are each located at a level the same as or higher than a level of a top surface of the gate capping pattern.

公开(公告)号：US20230163171A1

公开(公告)日：2023-05-25

申请号：US18102204

申请日：2023-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Jun KIM ,  Woong Sik NAM ,  Mirco CANTORO

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/0673 ,  H01L29/4236 ,  H01L29/6656 ,  H01L21/823481

Abstract: A semiconductor device includes first and second active patterns, a field insulating film between the first and second active patterns, a first gate structure intersecting the first active pattern and including a first gate electrode and a first gate spacer, a second gate structure intersecting the second active pattern and including a second gate electrode and a second gate spacer, a gate separation structure on the field insulating film between the first and second gate structures, the gate separation structure including a gate separation filling film on a gate separation liner, and a connecting spacer between the gate separation structure and the field insulating film, the connecting spacer protruding from a top surface of the field insulating film, and the gate separation liner contacting the connecting spacer and extending along a top surface and sidewalls of the connecting spacer and along the top surface of the field insulating film.

公开(公告)号：US20220415887A1

公开(公告)日：2022-12-29

申请号：US17570979

申请日：2022-01-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Jun KIM ,  Hyungjin PARK

IPC: H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device including a substrate; gate structures spaced apart from each other on the substrate, each gate structure including a gate electrode and a gate capping pattern; source/drain patterns on opposite sides of the gate structures; first isolation patterns that respectively penetrate adjacent gate structures; and a second isolation pattern that extends between adjacent source/drain patterns, and penetrates at least one gate structure, wherein each first isolation pattern separates the gate structures such that the gate structures are spaced apart from each other, the first isolation patterns are aligned with each other, and top surfaces of the first and second isolation patterns are each located at a level the same as or higher than a level of a top surface of the gate capping pattern.

公开(公告)号：US20240162311A1

公开(公告)日：2024-05-16

申请号：US18225777

申请日：2023-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Darong OH ,  Ho-Jun KIM ,  Jeewoong KIM

IPC: H01L29/417 ,  H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L23/481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device comprising a substrate including an active pattern, a channel pattern and a source/drain pattern that are on the active pattern, the source/drain pattern connected to the channel pattern, a gate electrode on the channel pattern, an active contact on the source/drain pattern, an upper contact being adjacent to the active contact and extending into the substrate, a lower power interconnection line buried in the substrate, and a power delivery network layer on a bottom surface of the substrate, wherein the lower power interconnection line includes a connection portion connected to the upper contact, and a lower portion of the upper contact protrudes into the connection portion.

公开(公告)号：US20230402382A1

公开(公告)日：2023-12-14

申请号：US18113715

申请日：2023-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Kyu KIM ,  Yun Suk NAM ,  Kyoung Woo LEE ,  Ho-Jun KIM ,  Da Rong OH ,  Sung Moon LEE ,  Hag Ju CHO ,  Seung Min CHA

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L23/5286 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/66439 ,  H01L29/42392

Abstract: A semiconductor device includes: a base substrate; a first interlayer insulating layer disposed on the base substrate; a power rail disposed inside the first interlayer insulating layer; an active pattern extended in a first horizontal direction and disposed on the first interlayer insulating layer; a gate electrode extended in a second horizontal direction different from the first horizontal direction and disposed on the active pattern; a gate cut extended in the first horizontal direction and disposed on the power rail, wherein the gate cut separates the gate electrode; and a power rail via disposed inside the gate cut, wherein the power rail via is overlapped by the power rail.