公开(公告)号：US20250022941A1

公开(公告)日：2025-01-16

申请号：US18904547

申请日：2024-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beomjin PARK ,  Dongwon KIM ,  Bongseok SUH ,  Daewon KIM

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device includes a first and second active regions extending in a first direction and having respective first and second widths in a second direction, the second width greater than the first width, a connection region connected to the first and second active regions and having a third width, between the first and second widths in the second direction, first and second gate structures respectively intersecting the first and second active regions and extending in the second direction, and a dummy structure intersecting at least a portion of the connection region, extending in the second direction, and between the first and second gate structures in the first direction. The dummy structure includes first and second pattern portions spaced apart from a side surface of the first gate structure by respective first and second distances in the first direction, the second distance greater than the first distance.

公开(公告)号：US20220320312A1

公开(公告)日：2022-10-06

申请号：US17568170

申请日：2022-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beomjin PARK ,  Dongwon KIM ,  Bongseok SUH ,  Daewon KIM

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/10

Abstract: A semiconductor device includes a first and second active regions extending in a first direction and having respective first and second widths in a second direction, the second width greater than the first width, a connection region connected to the first and second active regions and having a third width, between the first and second widths in the second direction, first and second gate structures respectively intersecting the first and second active regions and extending in the second direction, and a dummy structure intersecting at least a portion of the connection region, extending in the second direction, and between the first and second gate structures in the first direction. The dummy structure includes first and second pattern portions spaced apart from a side surface of the first gate structure by respective first and second distances in the first direction, the second distance greater than the first distance.

公开(公告)号：US20220173214A1

公开(公告)日：2022-06-02

申请号：US17371582

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Noh Yeong PARK ,  Dong Il BAE ,  Beomjin PARK

IPC: H01L29/10 ,  H01L27/092 ,  H01L29/16 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8238

Abstract: Disclosed are semiconductor devices and/or method of fabricating the same. The semiconductor device comprises a substrate including first and second regions, a first active pattern on the first region and including a pair of first source/drain patterns and a first channel pattern including first semiconductor patterns, a second active pattern on the second region and including a pair of second source/drain patterns and a second channel pattern including second semiconductor patterns, a support pattern between two vertically adjacent first semiconductor patterns, and a first gate electrode and a second gate electrode on the first channel pattern and the second channel pattern. A channel length of the first channel pattern is greater than that of the second channel pattern. A ratio of a width of the support pattern to the channel length of the first channel pattern is in a range of 0.05 to 0.2.

公开(公告)号：US20240096995A1

公开(公告)日：2024-03-21

申请号：US18231841

申请日：2023-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomjin PARK ,  Myunggil KANG ,  Dongwon KIM ,  Younggwon KIM ,  Hyumin YOO ,  Soojin JEONG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device, may include an active region extending in a first direction; a plurality of channel layers on the active region to be spaced apart from each other; a gate structure, surrounding the plurality of channel layers, respectively; and source/drain regions on the active region on at least one side of the gate structure, and contacting the plurality of channel layers, wherein the gate structure may include an upper portion on an uppermost channel layer among the plurality of channel layers and lower portions between each of the plurality of channel layers in a region vertically overlapping the plurality of channel layers, wherein a width of each of the plurality of channel layers in the first direction may be less than a width of lower portions of the gate structure, adjacent to the respective channel layers among the lower portions of the gate structure in the first direction.

公开(公告)号：US20210313442A1

公开(公告)日：2021-10-07

申请号：US17060193

申请日：2020-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongseok SUH ,  Daewon KIM ,  Beomjin PARK ,  Sukhyung PARK ,  Sungil PARK ,  Jaehoon SHIN ,  Bongseob YANG ,  Junggun YOU ,  Jaeyun LEE

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/10

Abstract: A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.

公开(公告)号：US20240321992A1

公开(公告)日：2024-09-26

申请号：US18531071

申请日：2023-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungpyo HONG ,  Beomjin PARK ,  Junggil YANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L2029/42388

Abstract: An integrated circuit device includes fin-type active regions extending in a first lateral direction on a substrate, a device isolation film covering sidewalls of the fin-type active regions, a gate line on the fin-type active regions and the device isolation film, nanosheet stacks on a fin top surface of each of the fin-type active regions, each nanosheet stack including at least one nanosheet and being surrounded by the gate line, a gate cut insulating portion on the device isolation film and facing an end sidewall of the gate line in a second lateral direction, and a corner insulating spacer between a first nanosheet stack of the nanosheet stacks and the gate cut insulating portion and between the device isolation film and the gate line, the first nanosheet stack being closest to the gate cut insulating portion in the second lateral direction.

公开(公告)号：US20240321884A1

公开(公告)日：2024-09-26

申请号：US18442590

申请日：2024-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inhyun SONG ,  Junggil YANG ,  Sangmoon LEE ,  Myunggil KANG ,  Jongsu KIM ,  Beomjin PARK

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is a semiconductor device including a substrate, a fin-type active region protruding on the substrate, a channel region on the fin-type active region and including a plurality of active patterns extending in a first horizontal direction and a semiconductor material layer, a gate line extending in a second horizontal direction that is perpendicular to the first horizontal direction and covering the channel region on the fin-type active region, and a pair of source/drain regions at both sides of the gate line on the fin-type active region, wherein a work function of the semiconductor material layer is different from a work function of the plurality of active patterns, the semiconductor material layer surrounds portions of the gate line between the plurality of active patterns, and the gate line is separated from the pair of source/drain regions with the semiconductor material layer therebetween.

公开(公告)号：US20220406919A1

公开(公告)日：2022-12-22

申请号：US17575856

申请日：2022-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomjin PARK ,  Myunggil Kang ,  Dongwon Kim ,  Keunhwi Cho

IPC: H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes: an active region extending on a substrate in a first direction; a plurality of semiconductor layers spaced apart from each other vertically on the active region, including a lower semiconductor layer and an uppermost semiconductor layer disposed above the lower semiconductor layer and having a thickness greater than that of the lower semiconductor layer; a gate structure extending on the substrate in a second direction, perpendicular to the first direction, and including a gate electrode at least partially surrounding each of the plurality of semiconductor layers; a spacer structure disposed on both sidewalls of the gate structure; and source/drain regions disposed on the active region on both sides of the gate structure and contacting the plurality of semiconductor layers.

公开(公告)号：US20220262790A1

公开(公告)日：2022-08-18

申请号：US17466043

申请日：2021-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jun KIM ,  Beomjin PARK ,  Dong Il BAE ,  Mirco CANTORO

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/423

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The semiconductor device includes a plurality of gate structures that are spaced apart from each other in a first direction on a substrate and extend in a second direction intersecting the first direction, and a plurality of separation patterns penetrating immediately neighboring ones of the plurality of gate structures, respectively. Each of the plurality of separation patterns separates a corresponding one of the neighboring gate structures into a pair of gate structures that are spaced apart from each other in the second direction. The plurality of separation patterns are spaced apart from and aligned with each other along the first direction.

公开(公告)号：US20240387527A1

公开(公告)日：2024-11-21

申请号：US18786756

申请日：2024-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jun KIM ,  Beomjin PARK ,  Dong Il BAE ,  Mirco CANTORO

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/423

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The semiconductor device includes a plurality of gate structures that are spaced apart from each other in a first direction on a substrate and extend in a second direction intersecting the first direction, and a plurality of separation patterns penetrating immediately neighboring ones of the plurality of gate structures, respectively. Each of the plurality of separation patterns separates a corresponding one of the neighboring gate structures into a pair of gate structures that are spaced apart from each other in the second direction. The plurality of separation patterns are spaced apart from and aligned with each other along the first direction.