公开(公告)号：US20210408028A1

公开(公告)日：2021-12-30

申请号：US17222403

申请日：2021-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGGIL KIM ,  KYENGMUN KANG ,  HYEEUN HONG

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11519

Abstract: An integrated circuit device includes a peripheral circuit structure arranged on a substrate, a gate stack arranged on the peripheral circuit structure and including a plurality of gate electrodes, and a dam structure formed in a dam opening portion that passes through the gate stack. The dam structure includes an insulation spacer on an inner wall of the dam opening portion and a pair of sloped sidewalls at an upper side of the dam opening portion, and a buried layer filling an inside of the dam opening portion and including an air space. The integrated circuit device further includes a mold gate stack surrounded by the dam structure and including a plurality of mold layers, a plurality of conductive lines arranged on the gate stack, and a plurality of through electrodes connected to the plurality of conductive lines, passing through the mold gate stack, and surrounded by the dam structure.

公开(公告)号：US20190081054A1

公开(公告)日：2019-03-14

申请号：US15981928

申请日：2018-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGGIL KIM ,  SANGSOO LEE ,  SEULYE KIM ,  HONGSUK KIM ,  JINTAE NOH ,  JI-HOON CHOI ,  JAEYOUNG AHN ,  SANGHOON LEE

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor memory device has a plurality of gates vertically stacked on a top surface of a substrate, a vertical channel filling a vertical hole that extends vertically through the plurality of gates, and a memory layer in the vertical hole and surrounding the vertical channel. The vertical channel includes a bracket-shaped lower portion filling part of a recess in the top of the substrate and an upper portion extending vertically along the vertical hole and connected to the lower channel. At least one end of an interface between the lower and upper portions of the vertical channel is disposed at a level not than that of the top surface of the substrate.

公开(公告)号：US20190333937A1

公开(公告)日：2019-10-31

申请号：US16509169

申请日：2019-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-HOON CHOI ,  SUNGGIL KIM ,  SEULYE KIM ,  HONGSUK KIM ,  PHIL OUK NAM ,  JAEYOUNG AHN

IPC: H01L27/11582 ,  H01L29/10 ,  H01L27/1157 ,  H01L29/06 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11565

Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.

公开(公告)号：US20210118907A1

公开(公告)日：2021-04-22

申请号：US17136851

申请日：2020-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon LEE ,  SUNGGIL KIM ,  SEULYE KIM ,  HWAEON SHIN ,  JOONSUK LEE ,  HYEEUN HONG

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/10 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L21/28

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The method comprises sequentially forming a sacrificial pattern and a source conductive layer on a substrate, forming a mold structure including a plurality of insulating layers and a plurality of sacrificial layers on the source conductive layer; forming a plurality of vertical structures penetrating the mold structure, forming a trench penetrating the mold structure, forming a sacrificial spacer on a sidewall of the trench, removing the sacrificial pattern to form a horizontal recess region; removing the sacrificial spacer, and forming a source conductive pattern filling the horizontal recess region.

公开(公告)号：US20190355741A1

公开(公告)日：2019-11-21

申请号：US16217696

申请日：2018-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANGHOON LEE ,  SUNGGIL KIM ,  SEULYE KIM ,  HWAEON SHIN ,  JOONSUK LEE ,  HYEEUN HONG

IPC: H01L27/11582 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/10 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The method includes sequentially forming a sacrificial pattern and a source conductive layer on a substrate, forming a mold structure including a plurality of insulating layers and a plurality of sacrificial layers on the source conductive layer; forming a plurality of vertical structures that penetrate the mold structure, forming a trench that penetrates the mold structure, forming a sacrificial spacer on a sidewall of the trench, removing the sacrificial pattern to form a horizontal recess region; removing the sacrificial spacer, and forming a source conductive pattern that fills the horizontal recess region.

公开(公告)号：US20180308859A1

公开(公告)日：2018-10-25

申请号：US15849121

申请日：2017-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-HOON CHOI ,  SUNGGIL KIM ,  SEULYE KIM ,  HONGSUK KIM ,  PHIL OUK NAM ,  JAEYOUNG AHN

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/06 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66553 ,  H01L29/66833 ,  H01L29/7926

Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.