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1.发明授权公开(公告)号：US11974401B2
公开(公告)日：2024-04-30
申请号：US17643003
申请日：2021-12-07
发明人： Sunghyup Lee , Chongo Yoon , Kwonho Son , Mincheol Seo , Yoonjung Kim , Hyungjin Kim , Jungsik Park , Sangyoup Seok , Donghun Shin , Seongyong An , Kyungjae Lee , Heeseok Jung , Huiwon Cho , Hyunju Hong
IPC分类号： H05K1/02 , H01Q1/36 , H01Q1/48 , H01Q3/34 , H01Q3/44 , H01Q7/00 , H01Q9/42 , H01Q13/10 , H01Q21/28 , H01Q21/30 , H05K1/11 , H05K1/14 , H05K1/18 , H05K5/04
CPC分类号： H05K1/189 , H05K1/118 , H05K1/141 , H05K1/147 , H05K2201/10098 , H05K2201/10189
摘要： An electronic device according to various embodiments may include: a first frame at least partially exposed to an outside of the electronic device and comprising a metal material, a flexible printed circuit board at least a portion of which is disposed adjacent to the first frame, a first connector electrically connecting the flexible printed circuit board and a main board of the electronic device, a bendable second connector electrically connecting the flexible printed circuit board and the first frame, a bolt including a bolt body extending through a groove formed in the second connector to be bolt-coupled to a bolt groove formed in the first frame and a bolt head formed integrally with the bolt body and disposed in a first direction with respect to the first frame, a plate disposed adjacent to the bolt head of the bolt and coupled to the first frame in the first direction to allow the bolt body of the bolt to be maintained in a state of being coupled to the bolt groove formed in the first frame, and an integrated circuit disposed on the flexible printed circuit board.
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公开(公告)号：US11837321B2
公开(公告)日：2023-12-05
申请号：US17372672
申请日：2021-07-12
发明人： Hyungjin Kim , Jungsik Park , Soongmann Shin
CPC分类号： G11C7/222 , G11C7/109 , G11C7/1045 , G11C7/1063 , G11C8/18
摘要： In an apparatus, a memory controller, a memory device, and a method for switching frequencies of clock signals to reduce power consumption, when the memory device performs an internal operation according to a command of the memory controller, a frequency of a clock signal of the memory controller is changed. The memory controller switches the frequency of the clock signal to a low frequency according to assertion of a status signal that indicates a busy operation status of the memory device according to the command, and switches the frequency of the clock signal to a high frequency according to de-assertion of the status signal that indicates a ready operation status of the memory device.
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公开(公告)号：US11747678B2
公开(公告)日：2023-09-05
申请号：US18068965
申请日：2022-12-20
发明人： Yoonki Park , Hyungjin Kim , Yongsung Yoo , Youngwook Jung , Minnyeong Han
IPC分类号： G02F1/1335 , G02F1/017 , G02F1/13357 , G02F1/137 , G02F1/35
CPC分类号： G02F1/133614 , G02F1/01791 , G02F1/133553 , G02F1/133603 , G02F1/133605 , G02F1/133617 , G02F1/13762 , G02F1/353 , G02F2202/046 , G02F2202/36
摘要： A display apparatus includes a liquid crystal panel; light sources configured to emit blue light; a reflective sheet including a first edge portion and a second edge portion, wherein a plurality of holes are disposed on the reflective sheet, the plurality of holes includes a first hole, a second hole, and a third hole, the first hole is disposed at a first distance from an edge of the first edge portion, the second hole is disposed at a second distance from the edge of the first edge portion, and the third hole is disposed at the first distance from the edge of the first edge portion, wherein the second distance is greater than the first distance; and pluralities of light conversion dots disposed around the first, second, and third holes, respectively, wherein the third hole is disposed on an overlap portion of the first and second edge portions.
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公开(公告)号：US11592711B2
公开(公告)日：2023-02-28
申请号：US17841165
申请日：2022-06-15
发明人： Yoonki Park , Hyungjin Kim , Yongsung Yoo , Youngwook Jung , Minnyeong Han
IPC分类号： G02F1/1335 , G02F1/13357 , G02F1/017 , G02F1/35 , G02F1/137
摘要： A display apparatus includes a liquid crystal panel; light sources configured to emit blue light; a reflective sheet including four edge portions and a first hole and a second hole on each of the four edge portions of the reflective sheet, the first hole disposed at a first distance from an edge of the reflective sheet, and the second hole disposed at a second distance from the edge of the reflective sheet, wherein the second distance is greater than the first distance; and first and second light conversion dots, wherein the first light conversion dots are disposed around the first hole of the reflective sheet, and the second light conversion dots are disposed around the second hole of the reflective sheet, wherein a size of each of the first light conversion dots is greater than a size of each of the second light conversion dots.
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公开(公告)号：US20220028431A1
公开(公告)日：2022-01-27
申请号：US17356080
申请日：2021-06-23
发明人： Hyungjin Kim , Yongjun Kim , Yonghun Kim , Minsu Ahn , Reum Oh , Jinyong Choi
IPC分类号： G11C5/06 , G11C5/02 , H01L25/065 , H01L23/538
摘要： A semiconductor device includes a cell area in which a plurality of memory cells are arranged in an array structure, and a peripheral area in which circuits configured to drive the memory cells are arranged, the peripheral area being next to the cell area. The cell area is divided into a plurality of banks, and the plurality of banks comprise first banks having a base size and second banks having a size of 1/(2*n) (wherein n is an integer greater than or equal to 1) of the base size. The plurality of banks are arranged in a first direction and a second direction perpendicular to the first direction, and the semiconductor device has a shape of a rectangular chip which is elongated in the second direction.
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公开(公告)号：US11158359B2
公开(公告)日：2021-10-26
申请号：US17178397
申请日：2021-02-18
发明人： Hyungjin Kim , Soong-Man Shin
摘要： A storage device includes a nonvolatile memory device, and a controller that exchanges a data signal with the nonvolatile memory device through a data input and output line and exchanges a data strobe signal with the nonvolatile memory device through a data strobe line. In a training operation, at least one of the nonvolatile memory device and the controller performs a coarse training of adjusting a delay of the data signal with a first stride and a fine training of adjusting the delay of the data signal with a second stride smaller than the first stride.
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公开(公告)号：US12019581B2
公开(公告)日：2024-06-25
申请号：US17936995
申请日：2022-09-30
发明人： Hyungjin Kim , Jinmyung Yoon , Youngmin Lee , Dasom Lee
IPC分类号： G06F15/80 , G06F12/02 , G06F12/0806 , G06F12/1045 , G06F13/16 , G06F15/163 , G06F15/167
CPC分类号： G06F15/80 , G06F12/023 , G06F12/0284 , G06F12/0806 , G06F12/1054 , G06F13/1663 , G06F15/163 , G06F15/167 , G06F2212/68
摘要： A multi-core processor includes a plurality of cores, a shared memory, a plurality of address allocators, and a bus. The shared memory has a message queue including a plurality of memory regions for transmitting messages between the plurality of cores. The plurality of address allocators are configured to, each time addresses in a predetermined range corresponding to a reference memory region among the plurality of memory regions are received from a corresponding core among the plurality of cores, control the plurality of memory regions to be accessed in sequence by applying an offset determined according to an access count of the reference memory region to the addresses in the predetermined range. The bus is configured to connect the plurality of cores, the shared memory, and the plurality of address allocators to one another.
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公开(公告)号：US11829224B2
公开(公告)日：2023-11-28
申请号：US17742175
申请日：2022-05-11
发明人： Dongyeon Park , Youngjae Park , Hyungjin Kim , Reum Oh , Jinyong Choi
IPC分类号： G06F1/00 , G06F1/3225 , G06F1/3296 , G06F1/3234 , G06F1/3203
CPC分类号： G06F1/3225 , G06F1/3275 , G06F1/3296 , G06F1/3203
摘要： In a method of operating a memory device, a first command to allow the memory device to enter an idle mode is received. A reference time interval is adjusted based on process, voltage and temperature (PVT) variation associated with the memory device. The reference time interval is used to determine a start time point of a power control operation for reducing power consumption of the memory device. A first time interval during which the idle mode is maintained is internally measured based on the first command. The power control operation is performed in response to the first time interval being longer than the reference time interval.
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公开(公告)号：US20220214582A1
公开(公告)日：2022-07-07
申请号：US17418664
申请日：2021-03-08
发明人： Yoonki PARK , Hyungjin Kim , Yongsung Yoo , Youngwook Jung , Minnyeong Han
IPC分类号： G02F1/1335 , G02F1/13357
摘要： A display apparatus includes a liquid crystal panel, and a light source apparatus configured to irradiate the liquid crystal panel with light. The light source apparatus includes a plurality of light sources configured to emit blue light, and a reflective sheet with a plurality of holes through which the light passes. The plurality of holes includes a first hole disposed at an edge portion of the reflective sheet, and a second hole in which a distance from an edge of the reflective sheet to the second hole is greater than a distance between the edge of the reflective sheet and the first hole and a plurality of first light conversion patches arranged along a circumference of a circle surrounding the first hole on the reflective sheet, and a plurality of second light conversion patches arranged along a circumference of a circle surrounding the second hole on the reflective sheet
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公开(公告)号：US20190122714A1
公开(公告)日：2019-04-25
申请号：US15995533
申请日：2018-06-01
发明人： Soong-Man SHIN , Hyungjin Kim , YoungWook Kim
摘要： A storage device including a nonvolatile memory device including memory blocks and a controller connected with the nonvolatile memory device through data input and output lines and a data strobe line may be provided. The nonvolatile memory device and the controller may be configured to perform training on the data input and output lines by adjusting a delay of a data strobe signal sent through the data strobe line and adjust delays of the data input and output lines based on the training result.
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