公开(公告)号：US20190043756A1

公开(公告)日：2019-02-07

申请号：US16016182

申请日：2018-06-22

Applicant: Renesas Electronics Corporation

Inventor： Mitsuhiro SUKEGAWA ,  Yoshinori MATSUMURO ,  Toshikazu HANAWA ,  Kentaro YAMADA

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/288

Abstract: To provide a semiconductor device capable of having improved adhesion between a plating film and a wiring layer. A method of manufacturing the semiconductor device includes a step of forming a wiring layer having a surface covered with an oxide film, a step of removing a portion of the oxide film by dry etching to form, in the oxide film, a first opening f exposing a portion of the wiring layer, a step of forming a passivation film covering the wiring layer, is provided with a second opening communicated with the first opening, and is made of an insulating resin material, and a step of growing a plating film on the wiring layer exposed from the first and second openings.

公开(公告)号：US20150311220A1

公开(公告)日：2015-10-29

申请号：US14679056

申请日：2015-04-06

Applicant: Renesas Electronics Corporation

Inventor： Shigeya TOYOKAWA ,  Michimoto KAMINAGA ,  Kentaro YAMADA

IPC: H01L27/115 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3105 ,  G11C16/12 ,  H01L21/02 ,  H01L21/28 ,  G11C16/14 ,  G11C16/08 ,  G11C16/26 ,  H01L29/788 ,  H01L21/311

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28167 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/31111 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11558 ,  H01L29/7883

Abstract: To enhance the write speed of a nonvolatile memory. A charge injection/emission part of a nonvolatile memory cell includes an active region having an upper face, a side wall, and a shoulder part connecting the upper face and the side wall, a conductor film covering the upper face and the shoulder part of the active region, and a capacitance insulating film provided between the conductor film and the active region. Furthermore, the active region has a protrusion part constituted of a first concave part with respect to the upper face and a second concave part with respect to the side wall, in the shoulder part.

Abstract translation: 提高非易失性存储器的写入速度。 非易失性存储单元的电荷注入/发射部分包括具有上表面，侧壁和连接上表面和侧壁的肩部的有源区，覆盖上表面和侧壁的上表面和肩部的导体膜 有源区和设置在导体膜和有源区之间的电容绝缘膜。 此外，有源区具有在肩部中由相对于上表面的第一凹部和相对于侧壁的第二凹部构成的突出部。

公开(公告)号：US20180108629A1

公开(公告)日：2018-04-19

申请号：US15844223

申请日：2017-12-15

Applicant: Renesas Electronics Corporation

Inventor： Kentaro YAMADA ,  Shigeki TOMARU ,  Taketoshi FUKUSHIMA

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/528

Abstract: To improve the reliability of a semiconductor device.The semiconductor device includes a plurality of wiring layers formed on a semiconductor substrate, a pad formed on an uppermost wiring layer of the plurality of wiring layers, a surface protection film which includes an opening on the pad and is made of an inorganic insulating film, a rewiring formed on the surface protection film; a pad electrode formed on the rewiring, and a wire connected to the pad electrode. The rewiring includes a pad electrode mounting portion on which the pad electrode is mounted, a connection portion which is connected to the pad, and an extended wiring portion which couples the pad electrode mounting portion and the connection portion, and the pad electrode mounting portion has a rectangular shape when seen in a plan view.

公开(公告)号：US20170287794A1

公开(公告)日：2017-10-05

申请号：US15630385

申请日：2017-06-22

Applicant: Renesas Electronics Corporation

Inventor： Toshikazu HANAWA ,  Kazuhide FUKAYA ,  Kentaro YAMADA

IPC: H01L21/66 ,  H01L21/768 ,  H01L23/522 ,  H01L21/311

CPC classification number: H01L22/26 ,  G01N21/68 ,  G01N21/73 ,  G01N21/84 ,  G01N2021/8411 ,  G01N2021/8427 ,  G01N2201/1247 ,  H01J37/32963 ,  H01J2237/334 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329

Abstract: A via hole is accurately formed in an interlayer insulating film over a metal wiring. Of emission spectra of plasma to be used for dry etching of the interlayer insulating film, the emission intensities of at least CO, CN, and AlF are monitored such that an end point of the dry etching of the interlayer insulating film is detected based on the emission intensities thereof.

公开(公告)号：US20160240499A1

公开(公告)日：2016-08-18

申请号：US15004983

申请日：2016-01-24

Applicant: Renesas Electronics Corporation

Inventor： Kentaro YAMADA ,  Shigeki TOMARU ,  Taketoshi FUKUSHIMA

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/06 ,  H01L23/5286 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03914 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05014 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05171 ,  H01L2224/05553 ,  H01L2224/05558 ,  H01L2224/05564 ,  H01L2224/05644 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48844 ,  H01L2224/49175 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/85206 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/35121

Abstract: To improve the reliability of a semiconductor device.The semiconductor device includes a plurality of wiring layers formed on a semiconductor substrate, a pad formed on an uppermost wiring layer of the plurality of wiring layers, a surface protection film which includes an opening on the pad and is made of an inorganic insulating film, a rewiring formed on the surface protection film; a pad electrode formed on the rewiring, and a wire connected to the pad electrode. The rewiring includes a pad electrode mounting portion on which the pad electrode is mounted, a connection portion which is connected to the pad, and an extended wiring portion which couples the pad electrode mounting portion and the connection portion, and the pad electrode mounting portion has a rectangular shape when seen in a plan view.

Abstract translation: 提高半导体器件的可靠性。 半导体器件包括形成在半导体衬底上的多个布线层，形成在多个布线层的最上布线层上的焊盘，表面保护膜，其在焊盘上包括开口，由无机绝缘膜制成， 在表面保护膜上形成重新布线; 在重新布线上形成的焊盘电极和连接到焊盘电极的电线。 重新配线包括焊盘电极安装部分，焊盘电极安装在该焊盘电极安装部分上，连接到焊盘的连接部分和连接焊盘电极安装部分和连接部分的延伸布线部分和焊盘电极安装部分 在平面图中看到的矩形。

公开(公告)号：US20170062288A1

公开(公告)日：2017-03-02

申请号：US15205069

申请日：2016-07-08

Applicant: Renesas Electronics Corporation

Inventor： Toshikazu HANAWA ,  Kazuhide FUKAYA ,  Kentaro YAMADA

IPC: H01L21/66 ,  H01L21/768 ,  G01N21/84 ,  H01L23/532 ,  G01N21/73 ,  H01L21/311 ,  H01L23/522

CPC classification number: H01L22/26 ,  G01N21/68 ,  G01N21/73 ,  G01N21/84 ,  G01N2021/8411 ,  G01N2021/8427 ,  G01N2201/1247 ,  H01J37/32963 ,  H01J2237/334 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329

Abstract: A via hole is accurately formed in an interlayer insulating film over a metal wiring. Of emission spectra of plasma to be used for dry etching of the interlayer insulating film, the emission intensities of at least CO, CN, and AlF are monitored such that an end point of the dry etching of the interlayer insulating film is detected based on the emission intensities thereof.

Abstract translation: 在金属布线上的层间绝缘膜中精确地形成通孔。 对于用于层间绝缘膜的干式蚀刻的等离子体的发射光谱，至少监测CO，CN和AlF的发射强度，使得基于层间绝缘膜的干蚀刻的终点被检测 发射强度。