公开(公告)号：US20140328113A1

公开(公告)日：2014-11-06

申请号：US14049312

申请日：2013-10-09

Applicant: QUALCOMM Incorporated

Inventor： Chiaming Chai ,  Shaoping Ge ,  Stephen Edward Liles ,  Kunal Garg

IPC: G11C11/413

CPC classification number: G11C11/413 ,  G11C7/1042 ,  G11C7/1075 ,  G11C7/12 ,  G11C11/412 ,  G11C11/419

Abstract: Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a SRAM data array of the SRAM. The SRAM also includes a pre-charge circuit provided in a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of the memory access request to avoid pre-charging bitlines in the SRAM data array during idle periods to reduce leakage power. The pre-charge circuit can enable pre-charging of the SRAM data array prior to data access such that the pre-charge circuit does not add latency to the first data access path.

Abstract translation: 本文公开的实施例包括用于在用于减少泄漏功率的数据访问之前在静态随机存取存储器（SRAM）中预充电位线的方法和装置。 存储器访问逻辑电路接收存储器访问请求，该存储器访问请求包括要在SRAM的SRAM数据阵列的第一数据访问路径中访问的数据输入地址。 SRAM还包括在第一数据访问路径外的第二数据访问路径中提供的预充电电路。 预充电电路被配置为使得SRAM数据阵列能够作为存储器访问请求的一部分进行预充电，以避免在空闲周期期间在SRAM数据阵列中预先充电位线以减少漏电功率。 预充电电路可以在数据访问之前对SRAM数据阵列进行预充电，使得预充电电路不会对第一数据存取路径增加等待时间。

公开(公告)号：US20170047930A1

公开(公告)日：2017-02-16

申请号：US14827125

申请日：2015-08-14

Applicant: QUALCOMM Incorporated

Inventor： Chiaming Chai ,  Shaoping Ge ,  Stephen Edward Liles ,  Chintan Hemendrakumar Shah

IPC: H03K19/0185 ,  H03K19/20

CPC classification number: H03K19/018528 ,  H03K3/356121 ,  H03K19/0963 ,  H03K19/20

Abstract: Dynamic voltage level shifters employing pulse generation circuits are disclosed. In one aspect, a dynamic voltage level shifter includes a dynamic voltage level shifting circuit. The dynamic voltage level shifting circuit includes a pre-charge circuit configured to provide supply voltage of a first voltage domain to a dynamic node in response to a clock signal having pre-charge voltage. An evaluate circuit is configured to provide ground voltage to the dynamic node in response to an input signal having an active voltage while the clock signal has evaluate voltage. A keeper circuit is configured to provide a reduced drive strength to the dynamic node in response to pulse signal. The pulse signal is generated by a pulse generation circuit, wherein a pulse width of the pulse signal correlates to a difference in supply voltages of first and second voltage domains.

Abstract translation: 公开了采用脉冲发生电路的动态电压电平移位器。 一方面，动态电压电平移位器包括动态电压电平移位电路。 动态电压电平移位电路包括预充电电路，其被配置为响应于具有预充电电压的时钟信号向动态节点提供第一电压域的电源电压。 评估电路被配置为当时钟信号具有评估电压时响应于具有有效电压的输入信号向动态节点提供接地电压。 保持器电路被配置为响应于脉冲信号向动态节点提供降低的驱动强度。 脉冲信号由脉冲发生电路产生，其中脉冲信号的脉冲宽度与第一和第二电压域的电源电压的差异相关。

公开(公告)号：US09190141B2

公开(公告)日：2015-11-17

申请号：US14064297

申请日：2013-10-28

Applicant: QUALCOMM Incorporated

Inventor： Chiaming Chai ,  Satendra Kumar Maurya

IPC: G11C11/00 ,  G11C11/412 ,  G11C7/20 ,  G11C11/417 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C7/20 ,  G11C11/417 ,  G11C11/419

Abstract: Circuits for voltage or current biasing static random access memory (SRAM) bitcells during SRAM reset operations are disclosed. Related systems and methods are also disclosed. To reset a plurality of SRAM bitcells in a single reset operation, a biasing circuit is provided and coupled to the plurality of SRAM bitcells. The biasing circuit is configured to apply a voltage or current bias to the SRAM bitcells during a reset operation after power provided to the SRAM bitcells is collapsed to a collapsed power level below an operational power level. The bias is applied as the power to the SRAM bitcells is restored to an operational power level, thus forcing the SRAM bitcells into a desired state. In this manner, the SRAM bitcells can be reset in a single reset operation without need for an increased drive strength from a reset circuit and without need to provide specialized SRAM bitcells.

Abstract translation: 公开了在SRAM复位操作期间用于电压或电流偏置静态随机存取存储器（SRAM）位单元的电路。 还公开了相关系统和方法。 为了在单个复位操作中复位多个SRAM位单元，提供偏置电路并耦合到多个SRAM位单元。 偏置电路被配置为在复位操作期间向SRAM位单元施加电压或电流偏置，其中提供给SRAM位单元的功率被折叠到低于操作功率电平的压缩功率电平。 当SRAM位单元的功率恢复到工作功率电平时，施加偏压，从而迫使SRAM位单元进入所需状态。 以这种方式，可以在单个复位操作中复位SRAM位单元，而不需要来自复位电路的增加的驱动强度，而不需要提供专门的SRAM位单元。

公开(公告)号：US20150036418A1

公开(公告)日：2015-02-05

申请号：US14064297

申请日：2013-10-28

Applicant: QUALCOMM Incorporated

Inventor： Chiaming Chai ,  Satendra Kumar Maurya

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C7/20 ,  G11C11/417 ,  G11C11/419

Abstract: Circuits for voltage or current biasing static random access memory (SRAM) bitcells during SRAM reset operations are disclosed. Related systems and methods are also disclosed. To reset a plurality of SRAM bitcells in a single reset operation, a biasing circuit is provided and coupled to the plurality of SRAM bitcells. The biasing circuit is configured to apply a voltage or current bias to the SRAM bitcells during a reset operation after power provided to the SRAM bitcells is collapsed to a collapsed power level below an operational power level. The bias is applied as the power to the SRAM bitcells is restored to an operational power level, thus forcing the SRAM bitcells into a desired state. In this manner, the SRAM bitcells can be reset in a single reset operation without need for an increased drive strength from a reset circuit and without need to provide specialized SRAM bitcells.

Abstract translation: 公开了在SRAM复位操作期间用于电压或电流偏置静态随机存取存储器（SRAM）位单元的电路。 还公开了相关系统和方法。 为了在单个复位操作中复位多个SRAM位单元，提供偏置电路并耦合到多个SRAM位单元。 偏置电路被配置为在复位操作期间向SRAM位单元施加电压或电流偏置，其中提供给SRAM位单元的功率被折叠到低于操作功率电平的压缩功率电平。 当SRAM位单元的功率恢复到工作功率电平时，施加偏压，从而迫使SRAM位单元进入所需状态。 以这种方式，可以在单个复位操作中复位SRAM位单元，而不需要来自复位电路的增加的驱动强度，而不需要提供专门的SRAM位单元。

公开(公告)号：US20140337573A1

公开(公告)日：2014-11-13

申请号：US14017760

申请日：2013-09-04

Applicant: QUALCOMM Incorporated

Inventor： Chiaming Chai ,  Shaoping Ge ,  Stephen E. Liles

IPC: G06F3/06

CPC classification number: G06F3/0689 ,  G06F3/0619 ,  G06F3/0665 ,  G11C29/785 ,  G11C29/848

Abstract: Embodiments disclosed include redirecting data from a defective data entry in memory to a redundant data entry prior to data access. Related systems and methods are also disclosed. The memory is configured to receive a memory access request. The received memory access request comprises a data entry address. The memory uses the data entry address to access data stored in a data array in the memory in a first data access path. It is possible that the rows or columns in the memory may be defective as a result of a manufacturing process. In the event that a row or column at the data entry address in the data array is defective, a data entry redirection circuit redirects the memory access request to a redundant row or column in the data array prior to data access.

Abstract translation: 所披露的实施例包括在数据访问之前将数据从存储器中的缺陷数据条目重定向到冗余数据条目。 还公开了相关系统和方法。 存储器被配置为接收存储器访问请求。 所接收的存储器访问请求包括数据输入地址。 存储器使用数据输入地址来访问存储在第一数据访问路径中的存储器中的数据阵列中的数据。 作为制造过程的结果，存储器中的行或列可能是有缺陷的。 在数据阵列中的数据输入地址上的行或列有缺陷的情况下，在数据访问之前，数据输入重定向电路将存储器访问请求重定向到数据阵列中的冗余行或列。

公开(公告)号：US09608637B2

公开(公告)日：2017-03-28

申请号：US14827125

申请日：2015-08-14

Applicant: QUALCOMM Incorporated

Inventor： Chiaming Chai ,  Shaoping Ge ,  Stephen Edward Liles ,  Chintan Hemendrakumar Shah

IPC: H03K19/20 ,  H03K19/0185

CPC classification number: H03K19/018528 ,  H03K3/356121 ,  H03K19/0963 ,  H03K19/20

Abstract: Dynamic voltage level shifters employing pulse generation circuits are disclosed. In one aspect, a dynamic voltage level shifter includes a dynamic voltage level shifting circuit. The dynamic voltage level shifting circuit includes a pre-charge circuit configured to provide supply voltage of a first voltage domain to a dynamic node in response to a clock signal having pre-charge voltage. An evaluate circuit is configured to provide ground voltage to the dynamic node in response to an input signal having an active voltage while the clock signal has evaluate voltage. A keeper circuit is configured to provide a reduced drive strength to the dynamic node in response to pulse signal. The pulse signal is generated by a pulse generation circuit, wherein a pulse width of the pulse signal correlates to a difference in supply voltages of first and second voltage domains.

公开(公告)号：US09442675B2

公开(公告)日：2016-09-13

申请号：US14017760

申请日：2013-09-04

Applicant: QUALCOMM Incorporated

Inventor： Chiaming Chai ,  Shaoping Ge ,  Stephen Edward Liles

IPC: G06F12/00 ,  G06F3/06 ,  G11C29/00

CPC classification number: G06F3/0689 ,  G06F3/0619 ,  G06F3/0665 ,  G11C29/785 ,  G11C29/848

Abstract: Embodiments disclosed include redirecting data from a defective data entry in memory to a redundant data entry prior to data access. Related systems and methods are also disclosed. The memory is configured to receive a memory access request. The received memory access request comprises a data entry address. The memory uses the data entry address to access data stored in a data array in the memory in a first data access path. It is possible that the rows or columns in the memory may be defective as a result of a manufacturing process. In the event that a row or column at the data entry address in the data array is defective, a data entry redirection circuit redirects the memory access request to a redundant row or column in the data array prior to data access.

Abstract translation: 所公开的实施例包括在数据访问之前将数据从存储器中的缺陷数据条目重定向到冗余数据条目。 还公开了相关系统和方法。 存储器被配置为接收存储器访问请求。 所接收的存储器访问请求包括数据输入地址。 存储器使用数据输入地址来访问存储在第一数据访问路径中的存储器中的数据阵列中的数据。 作为制造过程的结果，存储器中的行或列可能是有缺陷的。 在数据阵列中的数据输入地址的行或列有缺陷的情况下，在数据访问之前，数据输入重定向电路将存储器访问请求重定向到数据阵列中的冗余行或列。

公开(公告)号：US09007817B2

公开(公告)日：2015-04-14

申请号：US14049312

申请日：2013-10-09

Applicant: QUALCOMM Incorporated

Inventor： Chiaming Chai ,  Shaoping Ge ,  Stephen Edward Liles ,  Kunal Garg

IPC: G11C11/00 ,  G11C11/413 ,  G11C7/12 ,  G11C11/412 ,  G11C11/419 ,  G11C7/10

CPC classification number: G11C11/413 ,  G11C7/1042 ,  G11C7/1075 ,  G11C7/12 ,  G11C11/412 ,  G11C11/419

Abstract: Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a SRAM data array of the SRAM. The SRAM also includes a pre-charge circuit provided in a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of the memory access request to avoid pre-charging bitlines in the SRAM data array during idle periods to reduce leakage power. The pre-charge circuit can enable pre-charging of the SRAM data array prior to data access such that the pre-charge circuit does not add latency to the first data access path.

Abstract translation: 本文公开的实施例包括用于在用于减少泄漏功率的数据访问之前在静态随机存取存储器（SRAM）中预充电位线的方法和装置。 存储器访问逻辑电路接收存储器访问请求，该存储器访问请求包括要在SRAM的SRAM数据阵列的第一数据访问路径中访问的数据输入地址。 SRAM还包括在第一数据访问路径外部的第二数据访问路径中提供的预充电电路。 预充电电路被配置为使得SRAM数据阵列能够作为存储器访问请求的一部分进行预充电，以避免在空闲周期期间在SRAM数据阵列中预先充电位线以减少漏电功率。 预充电电路可以在数据访问之前对SRAM数据阵列进行预充电，使得预充电电路不会对第一数据存取路径增加等待时间。

公开(公告)号：US09911472B1

公开(公告)日：2018-03-06

申请号：US15362795

申请日：2016-11-28

Applicant: QUALCOMM Incorporated

Inventor： Shaoping Ge ,  Chiaming Chai ,  Stephen Edward Liles ,  Manish Garg

IPC: G11C7/12 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C7/12 ,  G11C5/14 ,  G11C7/1006 ,  G11C7/1096 ,  G11C7/18 ,  G11C7/22

Abstract: Systems and methods are directed to managing signals in a dual voltage domain comprising a high voltage domain and a low voltage domain. A write bitline driver circuit receives complementary global write bitline signals as input signals from a global write bitline driver in the low voltage domain, and a write enable signal as an input signal in the high voltage domain. The write bitline driver circuit generates complementary local write bitline signals as output signals in the high voltage domain for activating bitlines of a memory bank in the high voltage domain. The complementary local write bitline signals are based on the complementary global write bitline signals, voltage level shifted from the low voltage domain to the high voltage domain and gated by the write enable signal.

公开(公告)号：US09548089B2

公开(公告)日：2017-01-17

申请号：US14742706

申请日：2015-06-18

Applicant: QUALCOMM Incorporated

Inventor： Stephen Edward Liles ,  Satendra Kumar Maurya ,  Kunal Garg ,  Chiaming Chai ,  Chintan Shah

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/06

CPC classification number: G11C7/22 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066

Abstract: An asynchronous memory includes a memory array, a sense amplifier, an output latch, and a controller. In response to a clock signal from an external circuit requesting a read operation, the controller provides the clock signal to the memory array to read data, and controls the sense amplifier and the output latch to provide the functionality of a flip-flop master and slave so that the read operation delay through the output latch to the external circuit is removed from a first read cycle of two sequential read cycles.

Abstract translation: 异步存储器包括存储器阵列，读出放大器，输出锁存器和控制器。 响应于来自外部电路的请求读取操作的时钟信号，控制器将时钟信号提供给存储器阵列以读取数据，并且控制读出放大器和输出锁存器以提供触发器主器件和从器件的功能 使得通过输出锁存器到外部电路的读操作延迟从两个顺序读周期的第一读周期中去除。