公开(公告)号：US09548089B2

公开(公告)日：2017-01-17

申请号：US14742706

申请日：2015-06-18

Applicant: QUALCOMM Incorporated

Inventor： Stephen Edward Liles ,  Satendra Kumar Maurya ,  Kunal Garg ,  Chiaming Chai ,  Chintan Shah

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/06

CPC classification number: G11C7/22 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066

Abstract: An asynchronous memory includes a memory array, a sense amplifier, an output latch, and a controller. In response to a clock signal from an external circuit requesting a read operation, the controller provides the clock signal to the memory array to read data, and controls the sense amplifier and the output latch to provide the functionality of a flip-flop master and slave so that the read operation delay through the output latch to the external circuit is removed from a first read cycle of two sequential read cycles.

Abstract translation: 异步存储器包括存储器阵列，读出放大器，输出锁存器和控制器。 响应于来自外部电路的请求读取操作的时钟信号，控制器将时钟信号提供给存储器阵列以读取数据，并且控制读出放大器和输出锁存器以提供触发器主器件和从器件的功能 使得通过输出锁存器到外部电路的读操作延迟从两个顺序读周期的第一读周期中去除。

公开(公告)号：US09007817B2

公开(公告)日：2015-04-14

申请号：US14049312

申请日：2013-10-09

Applicant: QUALCOMM Incorporated

Inventor： Chiaming Chai ,  Shaoping Ge ,  Stephen Edward Liles ,  Kunal Garg

IPC: G11C11/00 ,  G11C11/413 ,  G11C7/12 ,  G11C11/412 ,  G11C11/419 ,  G11C7/10

CPC classification number: G11C11/413 ,  G11C7/1042 ,  G11C7/1075 ,  G11C7/12 ,  G11C11/412 ,  G11C11/419

Abstract: Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a SRAM data array of the SRAM. The SRAM also includes a pre-charge circuit provided in a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of the memory access request to avoid pre-charging bitlines in the SRAM data array during idle periods to reduce leakage power. The pre-charge circuit can enable pre-charging of the SRAM data array prior to data access such that the pre-charge circuit does not add latency to the first data access path.

Abstract translation: 本文公开的实施例包括用于在用于减少泄漏功率的数据访问之前在静态随机存取存储器（SRAM）中预充电位线的方法和装置。 存储器访问逻辑电路接收存储器访问请求，该存储器访问请求包括要在SRAM的SRAM数据阵列的第一数据访问路径中访问的数据输入地址。 SRAM还包括在第一数据访问路径外部的第二数据访问路径中提供的预充电电路。 预充电电路被配置为使得SRAM数据阵列能够作为存储器访问请求的一部分进行预充电，以避免在空闲周期期间在SRAM数据阵列中预先充电位线以减少漏电功率。 预充电电路可以在数据访问之前对SRAM数据阵列进行预充电，使得预充电电路不会对第一数据存取路径增加等待时间。

公开(公告)号：US20140328113A1

公开(公告)日：2014-11-06

申请号：US14049312

申请日：2013-10-09

Applicant: QUALCOMM Incorporated

Inventor： Chiaming Chai ,  Shaoping Ge ,  Stephen Edward Liles ,  Kunal Garg

IPC: G11C11/413

CPC classification number: G11C11/413 ,  G11C7/1042 ,  G11C7/1075 ,  G11C7/12 ,  G11C11/412 ,  G11C11/419

Abstract: Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a SRAM data array of the SRAM. The SRAM also includes a pre-charge circuit provided in a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of the memory access request to avoid pre-charging bitlines in the SRAM data array during idle periods to reduce leakage power. The pre-charge circuit can enable pre-charging of the SRAM data array prior to data access such that the pre-charge circuit does not add latency to the first data access path.

Abstract translation: 本文公开的实施例包括用于在用于减少泄漏功率的数据访问之前在静态随机存取存储器（SRAM）中预充电位线的方法和装置。 存储器访问逻辑电路接收存储器访问请求，该存储器访问请求包括要在SRAM的SRAM数据阵列的第一数据访问路径中访问的数据输入地址。 SRAM还包括在第一数据访问路径外的第二数据访问路径中提供的预充电电路。 预充电电路被配置为使得SRAM数据阵列能够作为存储器访问请求的一部分进行预充电，以避免在空闲周期期间在SRAM数据阵列中预先充电位线以减少漏电功率。 预充电电路可以在数据访问之前对SRAM数据阵列进行预充电，使得预充电电路不会对第一数据存取路径增加等待时间。